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I'm using Xilinx ISE and generated a memory using the CORE Generator & Architecture Wizard.

The problem is that it created a write enable signal (wea) as a STD_LOGIC_VECTOR(0 downto 0) and that results in a type mismatch:

Line ###: Type error near encnt ; current type std_logic; expected type std_logic_vector

How can I cast encnt, which is std_logic, to a one bit std_logic_vector?

(ISE doesn't allow me to change wea from the file of memory.)

mark_infinite
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  • Please show the code – JHBonarius Apr 16 '18 at 11:11
  • The VHDL term is type conversion (IEEE Std 1076-2008, 9.3.6 Type conversions) where type std_logic (a scalar type) and std_logic_vector (an array type) are not compatible, prompting scary_jeff's use of element association (6.5.6.3 Port clauses, 6.5.7 Association lists). –  Jun 29 '18 at 20:39

1 Answers1

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This is a pretty common scenario with these IP blocks. You can easily associate your std_logic signal like this:

wea(0) => encnt,

Instead of associating wea as a whole, you are just associating that one element (0). As wea only has one element, this assigns the whole vector.

scary_jeff
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    Or `wea <= "" & encnt`. – JHBonarius Apr 16 '18 at 11:10
  • Or an aggregate: `wea <= (0 => encnt);` noting that for the special case of a single element, only named association works, since positional association is indistinguishable from parentheses around an expression. –  Apr 16 '18 at 19:36