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I'm studying a vhdl design downloaded from internet. Some input/output ports are declared as std_logic_vector(0 downto 0). I don't understand what's the difference between std_logic_vector(0 downto 0) and std_logic. Does it have to do with some optimization? When would you use one instead of the other one?

Thank you.

Alexis
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  • They are two different types. Just try to convert either to `unsigned`. In C it would be the difference between an object of int and an array of int. – JHBonarius Jun 29 '18 at 16:49
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    One is a scalar type (base type std_ulogic) and one is a single dimensional array type who's element type happens to have the same base type. When you see ports declared as single element vectors it's generally because they're on generated source code allowing widths down to one or because someone is interfacing to a signal that can have a width of one. –  Jun 29 '18 at 19:40
  • @ user1155120. Thank you. Now it is clear. – Alexis Jun 29 '18 at 19:46
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    Duplicate of [Connecting a STD\_LOGIC to a one bit STD\_LOGIC\_VECTOR](https://stackoverflow.com/questions/49851974/connecting-a-std-logic-to-a-one-bit-std-logic-vector) –  Jun 29 '18 at 20:41

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The code you found might be generated automatically, so mostly many ventures give ability to change the width of ports. To generate this code they have some template and to make their template configurable they create ability to change some static variables. For example, they write it as std_logic_vector(m-1 downto 0) and user can change m in GUI, so if user puts m=1, the auto generated code will has std_logic_vector(0 downto 0).

Daniil Smirnov
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