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I want to use the clock of the BASYS 3 for my project. When I search for the constraint of the Project I found the following code:

set_property PACKAGE_PIN W5 [get_ports clk] 
set_property IOSTANDARD LVCMOS33 [get_ports clk] 
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]

Could someone explain it to me? I know clk is the input for the clock but in the last line what should I do? Should I change anything? Also what period 10.00 and waveform{0 5} means? Could you please help me?

dur
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user6210457
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1 Answers1

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These lines are Xilinx Design Constraints (XDC), which are a flavor of Synopsys Design Constraints (SDC).

First you shout distinguish between physical constraints (line 1-2) and timing constraints (line 3). These are required at different steps in the design flow.

set_property PACKAGE_PIN W5 [get_ports clk]

This lines connect your top-level port clk to pin W5.

set_property IOSTANDARD LVCMOS33 [get_ports clk]

This line sets the I/O standard needed by timing analysis for the rise and fall times at the pin, resulting in a setup/hold time window

create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]

This defines a clock signal of 100 MHz with 50% duty cycle for wire clk. If you need to refer to this clock in another statement, you can use the name sys_clk_pin.

Paebbels
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