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Questions tagged [zynq]

Zynq refers to the Zynq-7000 family of SoCs. A Zync device is a fully featured ARM processor-based system-on-chip.

Zynq refers to Zynq-7000 All Programmable SoCs which are based on the Xilinx All programmable SoC architecture. They enable extensive system level differentiation, integration, and flexibility through hardware, software, and I/O programmability.

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fatal error: sqlite3.h: No such file or directory

I'm trying to build a C application through cross compiling for a Zynq board (ARM architecture). When I type make without mentioning the ARM arch, it works fine on my laptop. But as soon as I modify the Makefile, I get an error saying: main.c:20:43:…
user2263752
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Understand U-Boot memory footprint

I don't understand what is happening in RAM when loading U-Boot. I'm working on a Xilinx Zynq ZC702 evaluation kit and I'm trying to load a Linux kernel on it using U-Boot. So I used the Xilinx tool Vivado and the SDK to generate a BOOT.bin file…
AwaX
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Flush cache to DRAM

I'm using a Xilinx Zynq platform with a region of memory shared between the programmable HW and the ARM processor. I've reserved this memory using memmap on the kernel command line and then exposed it to userspace via mmap/io_remap_pfn_range calls…
Brian Magnuson
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Using multiple core on Zynq

Until today I was programming on a single core, now I need to run my codes on multiple core. I'm researching for about 1 week and had some questions about this. I'm using Zynq 702, Arm DS-5 and Dstream by the way. And I'm trying to achive this while…
Yunus Yurtturk
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Embedded Linux on Zynq 7000, dropping almost all UDP packets

I am working with the Xilinx distribution of Linux on a Zynq 7000 board. This has two ARM processors, some L2 cache, a DRAM interface, and a large amount of FPGA fabric. Our appliance collects data being processed by the FPGA and then sends it…
Timothy Miller
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How to send data to AXI-Stream in Zynq from software tool?

I'm looking for a way to send some data from my software app written in C to AXI-Stream interface of Zynq. Something like open(/dev/axistream); send_data(data); I'm running Linux on the Arm part and now I want to connect it to the programmable…
Viktor Puš
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Vivado, Zynq, BRAM Controller, Narrow AXI burst option

Consider a simple system with PS (Processor system) with enabled AXI3 Master, connected to AXI4 Interconnect connected to BRAM Controller that has access to BRAM memory. What is the meaning of AXI Narrow Bursts? How do i define or consider what is…
CJC
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AXI Protocol, difference between secure and non-secure transactions

Just wanted to ask, what is the difference between secure and non-secure transactions when it comes to AXI bus transactions? What are the performance implications of either transaction?
CJC
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Filo I/O operations from SD card in Xilinx Zynq ZCU102

I'm using a Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit. I want to run a C++ program in the Xilink SDK tool(running on a Windows machine) that can do Filo I/O operations on a binary file stored in the SD card in the Zync board. I have the…
Naveen
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OpenCL for custom systems on SoC prototyping board

Is it possible to run OpenCL on a system designed by a user on a SoC prototyping board? To be more specific, I have a ZedBoard (Xilinx Zynq) that has Dual ARM cores and a Programmable Logic (PL) Area. If I design a simple system of my own that has a…
Haq100
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how to implement FPGA coprocessing with C/C++ on zynq 7020?

I'm studying vivadoHLS, and the tutorial u871 has introduced how to use HLS, and optimize my C/C++ code. But I want to know how to load them into my board zynq 7020, let it run on board. What I want to implement is : The host (CPU on board) calls…
happybunnie_wy
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Is there a way to synchronize custom interrupt signals with AXI master transactions in Vitis HLS?

I have been unable to find an answer, possibly due to me being unable to put specific enough nomenclature on the involved processes. I use Vitis HLS to synthesize designs where one call of the main function is one clock cycle long, being pipelined…
PhilMasteG
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How can I force a cache flush for a process from a Linux device driver?

I'm working on a research project that requires me to perform a memory capture from custom hardware. I am working with a Zedboard SoC (dual-core ARM Cortex-A9 with FPGA fabric attached). I have designed a device driver that allows me to perform…
ngc6027
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Vivado infers incorrect FREQ_HZ for AXI busses to my module

I'm working on a design in Vivado. My top level design is a block diagram. The block diagram has IP blocks and my Verilog RTL modules. Whenever I change my main module and Verilog updates the block diagram, it always incorrectly infers the clock…
Ethan Reesor
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TrustZone GCC example (Cortex A9 - ZedBoard Zynq 7000)

I am trying to run a simple TrustZone example on the ZedBoard, just a bare metal program that switches between Secure World and Normal World. Are any such examples available for the GCC compiler? The official ARM example is written mostly in ARM…
entipck
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