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Questions tagged [xilinx-edk]

The Embedded Development Kit (EDK) is an integrated development environment for designing embedded processing systems. This pre-configured kit includes Xilinx Platform Studio and the Software Development kit, as well as all the documentation and IP that you require for designing Xilinx Platform FPGAs with embedded PowerPC® hard processor cores and/or MicroBlaze™ soft processor cores.

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Filo I/O operations from SD card in Xilinx Zynq ZCU102

I'm using a Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit. I want to run a C++ program in the Xilink SDK tool(running on a Windows machine) that can do Filo I/O operations on a binary file stored in the SD card in the Zync board. I have the…
Naveen
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Problems with inclusion of C header file with automatically generated makefile

I have started to develop the C language software in the Xilinx Vitis IDE which Eclipse based. Organization of my project is following: -Application -Drivers -drivers -Adc -Pwm -Pwm.c -Pwm.h -Utils -Bits.h -Maths.h All the directories…
Steve
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Failed to open JTAG cable

I'm using an Atlys Spartan-6 xc6slx45 board. I am unable to burn the bit file using SDK. When I try to program FPGA it shows these errors: Program FPGA failed Connection to Board Failed Failed to Open JTAG Cable Cable target is not…
Classe Ensi E
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Maximum Length of Octet String allowed to send from SNMP Agent using LWIP

I am trying to implement SNMP agent on a device using LWIP Library in Xilinx SDK. I successfully implemented the agent and got the agent running over my device to respond to commands (snmpget, snmpset,snmpwalk). But if a OID has to return an octet…
mano49j
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How to access Xilinx Axi DMA from Linux?

I'm a software developer but I'm a newbie to embedded software development. I have a Zynq Ultrascale board that has an Axi DMA in its Hardware and I want to access this DMA from Linux. I know I should use DMA-Engine to Access DMA in Linux and I…
hamed
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Xilinx FPGA Error :FPGA Programming Failed due to errors while initializing bitstream

I have a problem in loading my program in FPGA ,I got this error: FATAL:Data2MEM:44 - Out of memory allocating 'getMemory' object of 960000000 bytes. Total memory already in use is 14823 bytes. Source file "../s/DeviceTableUtils.c", line…
Ghizlane
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Generate bitstream without vendor specific IDE

What I am trying to achieve is to synthesize very simplistic vhdl to bitstream and test on a proto board. Actually language does not matter. Anyone achieved so far so that you can directly generate bit from any form of code without the requirement…
user10099390
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control icap in Partial Reconfiguration

I'm going to implement partial reconfiguration on virtex5 Xilinx Board. I've written 3 modules(top module and up-counter and down-counter) and created bit streams by Plan-ahead.The result is shown by 2 LEDs(up or down count). My problem is how to…
nasir khani
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Running Xilinx Command line Tools - XST does not work

I'm currently working on a project that students can hand in their xilinx projects via e-mail and i will Synthesis, Place and Route and generate a bitstream which then should be uploaded to an FPGA. So first things first. I installed the ISE Tools…
nablahero
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Error in generate programming file in xilinx EDK

while working on Xilinx EDK to implement a simple design using embedded softcore IP, we have hit a few hurdles, following is the detailed outline of the problems we are facing. as per our understanding, we followed the following steps involved for…
Himanshu Sourav
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I2c Master testing on FPGA board

I have implemented i2c master code for reading temperature value from temp sensor(slave).i am testing my code on FPGA evolution board.FPGA is Microsemi nano very basic FPGA.How can I test my master without connecting to the slave device?
Kanika Sharma
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Xilinx SDK is not updated by μblaze parameters

I have modified the "system.mhs" file as follows : begin microblaze // some lines of code PARAMETER C_PVR = 2 PARAMETER C_PVR_USER1 = 0x02 PARAMETER C_PVR_USER2 = 0x0bb35 //some lines of code End when i build the hardware in Xps and export to…
IbrahimShazly
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How to change default/Active build configuration from 'Debug' on workspace launch?

I have multiple custom Build Configurations in my project as shown below: Screenshot of build configurations On workspace setup by default it opens up in 'Debug' configuration. I must have this changed to 'Rev8 Release' (one of my custom…
jasmin maria
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xil_cache error in Xilinx SDK

I am working on a small project of mine on Digilent Atlys and after all of the standard generating the netlist and bitstream, and exporting to SDK, I happen to get a weird error which states that the xil_cache.h is not present anywhere (even though…
Joe Carr
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Programming cable for Papilio Pro

I want to buy a Papilio Pro. For programming this FPGA, I need a cable. I can use a Xilinx programming cable or others cable which are cheaper like this cable. I suppose with Xilinx programming cable, I can use Xilinx programmer kit. It is possible…
Azwaw
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