Questions tagged [axi4]
10 questions
5
votes
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Vivado, Zynq, BRAM Controller, Narrow AXI burst option
Consider a simple system with PS (Processor system) with enabled AXI3 Master, connected to AXI4 Interconnect connected to BRAM Controller that has access to BRAM memory.
What is the meaning of AXI Narrow Bursts? How do i define or consider what is…
CJC
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5
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1 answer
AXI Protocol, difference between secure and non-secure transactions
Just wanted to ask, what is the difference between secure and non-secure transactions when it comes to AXI bus transactions?
What are the performance implications of either transaction?
CJC
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4
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1 answer
Is there a way to synchronize custom interrupt signals with AXI master transactions in Vitis HLS?
I have been unable to find an answer, possibly due to me being unable to put specific enough nomenclature on the involved processes.
I use Vitis HLS to synthesize designs where one call of the main function is one clock cycle long, being pipelined…
PhilMasteG
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4
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1 answer
AXI4-Stream Position Bytes
Can someone explain what a position byte is in the context of the AXI4-Streaming interface? I don't understand how, while it's not the same as a null byte, it doesn't have to transmitted to the slave.
sheridp
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3
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1 answer
Xilinx, Zynq, AXI4 interconnect. What are the performance implications of configuring register slice and data fifo options?
Consider an AXI4 Interconnect on the PL (FPGA) side.
When I double click to see the available options, there is a tab in Slave interfaces. Containing the following options.
What is the purpose of enabling register slice? Does outer refer to the…
CJC
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2
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1 answer
AXI4 delay transactions
I am just looking for advice. I currently have a custom IP integrated in VHDL which has a AXI4 slave input and an AXI4 master output, and currently the signals are directly tied together.
I would like to add a customizable latency to the AXI…
MateoConLechuga
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1
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1 answer
using rocket chip(a library of chisel) to generate a axi4crossbar in verilog language
I want to use rocket chip to generate a axi4crossbar with 2 slave ports and 1 master port, here is my chisel source code
package empty
import chipsalliance.rocketchip.config.{Config, Parameters}
import chisel3._
import…
xlgforever
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MicroBlaze AXI4 Exceptions
I am wondering about Data Bus Exceptions for the MicroBlaze. In the MicroBlaze product manual it states that the exception can only occur on M_AXI_DC when the cache is turned off? This doesn't make sense to me; does it mean that if an error response…
MateoConLechuga
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0
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How can AXI4 support PCIE Producer/Consumer ordering model?
PCIE uses Producer/Consumer ordering model, but AXI4 uses a different ordering model. AXI4's read and write channels are independent.
For instance, a system like this,
CPU <-> PCIE Controller <-> PCIE AXI Bridge <-> AXI4 with DEC and DDR slaves (DEC…
Zhibo Shen
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AXI4 AxVALID high in same clock
I have been looking for some documentation on the case when ARVALID and AWVALID both go high in the same clock and contain the same address. Should the write be handled first, or should the read? Any help is much appreciated.
MateoConLechuga
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