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Questions tagged [amba]

The ARM Advanced Microcontroller Bus Architecture (AMBA) encompasses (among others) the APB, AHB and AXI interconnect types, commonly seen on ARM processors.

Specifications can be found here.

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L1 cache ports in ARM Cortex processors

I did some reseach, but could not find much information. I'd like to know how many L1 read and L1 write ports ARM embedded processors have and how wide the ports are. Specifically, I am interested in Cortex-A8, Cortex-A9, and Cortext-A15. My blind…
aminfar
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Explaination of ARM (especifically mobile) Peripherals Addressing and Bus architecture?

I will first say that I'm not expert in the field and my question might contain misunderstanding, in which case, I'll be glad if you correct me and attach resources so I can learn further details. I'm trying to figure out the way that the system…
Bush
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Any built-in Linux methods for AXI-burst type devices?

I need to communicate with an FPGA device based on an AXI-burst interface. What are the ways to access such a device through Linux without involving a DMA? Burst is an intrinsic property of the AXI standard, which should typically be triggered…
Stark07
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AXI4-Stream Position Bytes

Can someone explain what a position byte is in the context of the AXI4-Streaming interface? I don't understand how, while it's not the same as a null byte, it doesn't have to transmitted to the slave.
sheridp
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How are bytes mapped to AXI4 bus on a little endian system

If a program running on a little endian processor writes the value 0xaabbccdd uncached to address 0, and the processor uses a 32-bit wide AXI4 bus, are bits 31-24 of WDATA 0xaa or 0xdd? AXI does not expose byte addressable memory--it can only read…
JeffB
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What's the minimum clock cycles number to read and write with AXI4Lite

I'm wondering what is the minimum number of clock cycle to do a simple access on an AXI4Lite bus. I think it's 4, but I'm not sure.
FabienM
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MT7621 Soc Crypto Engine - IRQ not mapped

I am using the latest Openwrt trunk firmware (kernel 4.3) and have successfully compiled the driver for its CryptoEngine, an internal ipsec accelerator of MT7621 Soc (which as far as I understood is on an internal bus called AMBA / APB). The driver…
fededim
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AXI4Lite slave IP

Is there any AXI4Lite slave IP (Verilog, VHDL) available under GNU GPL? I want to test a virtual AXI4 master in a uP system and hence this requirement. Just an AXI4 slave or AXI3 slave will also do (I can strip down the signals to make it AXI4Lite…
dpaul
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I am trying to understand the way I can write a UVM scoreboard for a DUT (arbiter) with multiple masters and one slave

I need to write a scoreboard for a DUT which has 3 AXI masters as input and one of them goes out on the other side to AXI slave, like 3 AXI masters-> DUT-> AXI slave. Please let me know if my understanding below is correct or are there any more ways…
Grace90
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Multi-master AXI interface connections

Do we need to have three instantiations of AXI master interface in top file if we have 3 AXI masters and then send these three interfaces to 3 AXI agent instantiations using the config_db? Or, how does it work in case of a multi-master scenario to…
Grace90
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APB Protocol vs Operating States conflict?

I'm having difficulty understanding the Operating State of the APB Protocol. In the diagram, the state ACCESS goes back to SETUP state when PREADY = 1 and there is a transfer. Also, it describes that The bus only remains in the SETUP state for one…
renvill
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How is AMBA ACE different from the AXI protocol?

What is the difference between ADVANCED MICROCONTROLER BUS ARCHITECTURE-ACE and ADVANCED MICROCONTROLER BUS ARCHITECTURE-AXI protocol?
vinaykumar
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MDMA & internal FLASH R/W on STM32H7

Good morning, We're using an STM32H7 to acquire simoultaneously 3 ADC channels 16-bit @ 5MSPS, and we store data in an external eMMC. Everything worth seamlessly as follow : 3 slave-SPI with 3 DMA to internal flip/flop buffers ; MDMA to interleave…
Clément G.
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Two master components controlling same slave (address assignation), Intel Quartus Prime Platform Designer (Qsys)

I am doing a project using DE1-SoC (FPGA + ARM cortex A9). You can see a part of the design (Qsys, platform designer) here An on chip memory (RAM, image_memory) is being mastered by two different masters. One of the masters is well known…
ANMOSI
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Enabled SDRAM bridge of Cyclone V is blocked

I've got a DE10-Nano Cyclone V development board with 1 GB of external DDR3 RAM from Terasic and I want to implement a driver, which can manage the communication between Linux running on the ARM Cortex-A9 processor and the FPGA fabric of the Cyclone…
Krustenkaese
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