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I'm wondering what is the minimum number of clock cycle to do a simple access on an AXI4Lite bus.

I think it's 4, but I'm not sure.

FabienM
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1 Answers1

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In theory, you can have single cycle (combinatorial) transaction, but that's not practical in most cases, so two cycles - one for address and one for data is the practical minimum. This ignores the B-channel in write, which is quite typical.

If you want to know what's the minimum in your IP, just tie READY signals to '1' and see what happens.

FritzDC
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