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Questions tagged [qsys]

Qsys is a system integration tool included as part of the Altera Quartus® II software.

Qsys is a system integration tool included as part of the Altera Quartus® II software. Qsys captures system-level hardware designs at a high level of abstraction and automates the task of defining and integrating customized HDL components, which may include IP cores, verification IP, and other design modules. Qsys facilitates design reuse by packaging and making available your custom components and systems, and integrates your custom components with Altera® and third-party developer components.

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How to enable SD card with Nios II MMU and Linux 4.9

I fetched and built the linux-socfpa for my Altera DE2-115. I used buildroot and u-boot to build it. It starts but there is no filesystem. I have an SD card plugged into the FPGA, is there some way I can use the SD card as a filesystem? System…
Niklas Rosencrantz
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Altera Qsys and top level entity with array of std_logic_vector

I have been trying to declare my type in a separate "mytypes.vhd" file as follows: library ieee; use ieee.std_logic_1164.all; package mytypes is type my_bus_array_type is array (0 to 3) of std_logic_vector(7 downto 0); end package mytypes; and…
kean
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Enumerating objects in all libraries inside QSYS.LIB

There is pretty much exhaustive info about tables (PF including PF-SRC,LF etc) resides in QSYS2.SYSTABLES. However when it comes to enumerating all objects (e.g. including PGM, SRVPGM,DTAQ,DTAARA and so on) in certain library do the single source of…
im_infamous
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Two master components controlling same slave (address assignation), Intel Quartus Prime Platform Designer (Qsys)

I am doing a project using DE1-SoC (FPGA + ARM cortex A9). You can see a part of the design (Qsys, platform designer) here An on chip memory (RAM, image_memory) is being mastered by two different masters. One of the masters is well known…
ANMOSI
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looking for Altera HPS to FPGA custom component integrations guideline using Qsys

I am looking for HPS to FPGA custom component integrations guideline using Qsys. I have De0 nano SoC board. I am new to SoC FPGA programming. I still could not found a material or tutorial for HPS to custom VHDL or Verilog component integration. I…
G.Ornill
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Access violation while compiling (synthesis step) in Quartus II with Qsys System

In Quartus II (V15.02) while compiling (step Analysis & Synthesis) I get the the following error when I assign the port map for the qsys design in my top entity: -------------------------------------------------------------- Problem…
Eggi
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Can QSys recurse through custom component, to generate IP?

I have a custom QSys component, that instantiates a couple of Altera IP. The Altera IP is also in the form of .qsys files. Is it possible to have Qsys recurse through my custom component and generate the instantiated IP for me? Currently I have to…
Jehandad
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How to use new component created in Qsys to vectorize/group together many signals

In the Qsys, I am using twelve input parallel ports (lets name them pio1 to pio12), each port is 12 bits. These parallel ports obtain values from the vhdl block in Quartus schematic. In the schematic bdf, I can see pio1 to pio12 from the nios ii…
user2563812
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How to vectorize/group together many signals generated from Qsys to Altera Quartus

In the Altera Qsys, I am using ten input parallel ports (lets name them pio1 to pio10), each port is 12 bits. These parallel ports obtain values from the vhdl block in Quartus schematic. In the schematic bdf, I can see pio1 to pio10 from the nios ii…
user2563812
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VHDL 2nd Ring Oscillator Using External Clock,

I am new to VHDL, so I have developed some code for a Ring Oscillator using the internal clock of my board, but I want to add a 2nd One using the internal clock, but I have some issues with understanding how to go by it. The first one works…
Anuel Abrah
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niosii processor Altera C program

I'm currently working on the Altera DE0 board with the QuartusII Web Edition software. I need to use a nios processor on Qsys to display a shifted signal from a GPIO pin on my board. The input signal would be a clock signal from an external source.…
Elyouss
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Communication between FPGA and Aria V HPS?

I want to make communication using Altera MM Mailbox IP component, between Aria V hps and my nios processors. Project in Qsys I managed to write down C code for Nios processors (FPGA side) to work with mailbox IP, then I made header file for HPS…
techno
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How do I get my returned data to format through a structure?

I'm sending this to the server: import requests response = requests.get('http://SERVER-IP/get.cgi?req=zones') print(response.content) I get back a string of data like…
Geoffrey Franklin
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How to implement a watchdog timer on a Cyclone II FPGA in quartus ii

I need to implement a watchdog timer on my Cyclone II FPGA board. I have designed the system using QSYS, i need to know what are the next steps to implement and test a watchdog Timer.
wi95
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Changing a Qsys design to run latest version of uClinux

I'm using a design in Qsys to run uClinux v2.6. I would like to run a newer Linx but I wa told that I must change the Qsys design and add another timer because newer Linux uses two timers. Is that correct and where can I find information about…
Niklas Rosencrantz
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