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Questions tagged [intel-fpga]

Intel FPGA - formally known as Altera - which is wholly owned subsidiary of Intel, is a major brand of Field Programmable Gate Arrays (FPGA).

Intel FPGA is a company part of Intel creating FPGAs and CPLD. It is a Xilinx competitor. Famous associated name are:

  • Stratix
  • Cyclone
  • Arria
  • MAX

It also offers intellectual properties like Nios II Processor, Hardware development programs like Quartus, software development programs like Nios Embedded Software.

This link points to various trainings that are free and offered by Intel FPGA.

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Programming VHDL on Linux?

Anyone knows good environment to program VHDL and simulate it (don't matter Xilinx or Altera) using Linux?
Daniel M.
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Altera Quartus Error (12007): Top-level design entity "alt_ex_1" is undefined

I've looked at all the previous questions and no one seems to have a problem as simple as mine. Also I've searched the web and can't find a solution. I'm new to VHDL and am trying to compile the simple example provided by Altera, which is as…
unplugngo
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Compile Date and Time in FPGA

Can I uses in VHDL something similar to the C-Sourcecode-Macros __DATE__ and __TIME__ to make the compile time available in the FPGA as a kind of version time stamp? As a >>>new-comer<<< to VHDL I want to modify the following existing code, which…
Helmholtz42
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Altera Quartus falsly says Modelsim isn't installed

Installed Quartus 13.0 with Modelsim in Fedora 22 64-bit. Running Quartus in 32-bit because I get lots and lots of problems otherwise. However, I can start Quartus, create a project, synthesize it, fire up the simulation window and configure the in…
Johan
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ModelSim-Altera error

I'm using Ubuntu Linux 14.04 LTS with Altera Quartus 15.0 web-edition and I'm having a hard time simulate my design due to licensing errors. I'm designing an LCD_driver for the VEEK-MT's LCD touch screen by terasic with the Cyclone IV EP4CE115 by…
Doron Behar
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VHDL assigning literals

I'm trying to use unsigned integers in VHDL with well defined bit widths. It seems VHDL does not like me trying to assign literal values to these types defined as: variable LCD_DATA: unsigned(19 downto 0) := 0; But in my IDE (Quartus), I get a…
Christopher Brown
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Execution time for loops

I'm analysing and measuring and getting different results fom my analysis and the measurement. The code is two loops with a data cache with a size of 512 bytes and a block size of 32 bytes: int SumByColRow (int matrix[M][M], int size) { int i, j,…
Niklas Rosencrantz
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Unable to lock chain (Insufficient port permissions)

I am new to Linux , and I am trying to install AlteraQuartus 2 WEb Edition and NIOS2 EDS to play with Nios2 Processor. However , after installing Quartus and when I am trying to execute jtagconfig. I do not see something like below , even after…
user2746930
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Checksum inside Altera FPGA .jic file

I'm modifying a firmware file (.jic) JTAG Indirect Configuration File with a small algorithm, but changing data inside the file makes it unusable because there is a checksum somewhere in the file that has to be updated. I need to find where is a…
denoise
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How to enable SD card with Nios II MMU and Linux 4.9

I fetched and built the linux-socfpa for my Altera DE2-115. I used buildroot and u-boot to build it. It starts but there is no filesystem. I have an SD card plugged into the FPGA, is there some way I can use the SD card as a filesystem? System…
Niklas Rosencrantz
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How to fix libXft.so.2: cannot open shared object file when simulating hardware in Quartus 20.1 running on Pop_OS 20.04

I have recently moved to Linux and am getting used to the OS, I managed to install and run Quartus 20.1 Lite and I was testing it out with an old working project. When I opened my waveform and ran the simulation I…
Kevin Propst
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Flash / Run Altera Cyclone IV with OpenOCD

I would like to run an Altera Cyclone IV IP with OpenOCD. No matter what file I need from quartus, but the execution should be done by OpenOCD. I am currently trying to do it with a sof file. The one that quartus uses for the programmer. Additional…
Cyborg-X1
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configfs do not mount device-tree/overlays

I'm working on a Cyclone V SOC FPGA from Altera with a double Cortex-A9 processor. The embedded system (linux 4.15.7) is created with Buildroot-2018.02. U-boot is used to load the system i-e FPGA.rbf file, device tree blob and zImage and everything…
grorel
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how to initialize ram of multiple instance with different contents in quartus

I designed a RAM module, and I need multiple instances of this module each with a different memory initialization file. The Quartus manual says that Quartus supports the $readmemh() function to initialize RAM. So I added two parameters to this…
paigu
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Cocotb VHDL need for FLI

I am currently setting up a Cocotb based verification environment. I just discovered that the example provided with Cocotb don't work in my case if using VHDL, because my simulator has no FLI (foreign language interface). I get the following…
user1654361
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