Questions tagged [quartus]

For questions about Quartus, a software tool developed by Altera / Intel to assist in the design, analysis, and synthesis of HDL designs, including FPGA and CPLD.

Quartus is a software tool produced by Altera / Intel for analysis and synthesis of HDL designs, which enables the developer to compile their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer.

The Quartus design software provides a complete, multiplatform design environment that easily adapts to specific design needs. It is a comprehensive environment for system-on-a-programmable-chip (SOPC) design. The Quartus software includes solutions for all phases of fpga and CPLD design.

Source: Quartus II User Manual

QuartusHelp contains documentation about the list of messages that can output Quartus during synthesis with their signification.

See also: altera

554 questions

votes

5 answers

Altera Quartus Error (12007): Top-level design entity "alt_ex_1" is undefined

I've looked at all the previous questions and no one seems to have a problem as simple as mine. Also I've searched the web and can't find a solution. I'm new to VHDL and am trying to compile the simple example provided by Altera, which is as…

vhdl intel-fpga quartus

asked Sep 14 '14 at 10:31

unplugngo

votes

1 answer

Altera Quartus falsly says Modelsim isn't installed

Installed Quartus 13.0 with Modelsim in Fedora 22 64-bit. Running Quartus in 32-bit because I get lots and lots of problems otherwise. However, I can start Quartus, create a project, synthesize it, fire up the simulation window and configure the in…

modelsim intel-fpga quartus

asked Sep 14 '15 at 07:12

Johan

5,003
3
36
50

votes

2 answers

ModelSim-Altera error

I'm using Ubuntu Linux 14.04 LTS with Altera Quartus 15.0 web-edition and I'm having a hard time simulate my design due to licensing errors. I'm designing an LCD_driver for the VEEK-MT's LCD touch screen by terasic with the Cyclone IV EP4CE115 by…

linux licensing modelsim intel-fpga quartus

asked Aug 09 '15 at 20:27

Doron Behar

2,606
2
21
24

votes

4 answers

How do I make Quartus II compile faster

I'm using Altera Quartus 2 to do a custom 8 bit processor and it takes forever to compile on my laptop. I'm only using simulations and making my processor in schematic (block diagram) and VHDL. Right now it takes around 10 minutes to compile, which…

vhdl quartus

asked Dec 10 '08 at 02:46

Hoffmann

14,369
16
76
91

votes

1 answer

Quartus II use file only in simulation

I want to run a simulation in Quartus. So I assign a Testbench in the Assignment menu. My testbench includes my DUT(D) and a extra component(E), which is only for simulation (so this component includes statements which are not syntesizeable). My…

vhdl modelsim quartus

asked Jan 16 '16 at 16:36

alabamajack

votes

1 answer

How to fix libXft.so.2: cannot open shared object file when simulating hardware in Quartus 20.1 running on Pop_OS 20.04

I have recently moved to Linux and am getting used to the OS, I managed to install and run Quartus 20.1 Lite and I was testing it out with an old working project. When I opened my waveform and ran the simulation I…

ubuntu quartus intel-fpga

asked Jul 03 '20 at 15:57

Kevin Propst

votes

0 answers

The globally static error (modelsim vs quartus)

This simple test leads to an error while compiling with modelsim whereas Quartus is fine to go through the whole synthesis/fitter process. library ieee; use ieee.std_logic_1164.all; entity submodule is port( four_bits_input : in …

vhdl modelsim quartus

asked May 17 '18 at 13:02

grorel

1,408
15
21

votes

2 answers

how to initialize ram of multiple instance with different contents in quartus

I designed a RAM module, and I need multiple instances of this module each with a different memory initialization file. The Quartus manual says that Quartus supports the $readmemh() function to initialize RAM. So I added two parameters to this…

verilog fpga intel-fpga quartus

asked Apr 03 '17 at 02:44

paigu

votes

1 answer

Object is used but not declared?

I have the following VHDL code, its a entity of a project: library ieee; use ieee.std_logic_1164.all; library work; use work.typedef.all; entity uc is port(faaaa: in std_logic_vector(15 downto 0); phi: in std_logic; …

vhdl quartus

asked May 29 '15 at 08:39

walidsarkis

votes

1 answer

How to concatenate strings with integer in report statement?

I'm having trouble getting the following report statement to work: report "ERROR: instruction address '" & CONV_INTEGER(a(7 downto 2)) & "' out of memory range." severity failure; Where a is of type in std_logic_vector(31 downto 0). The error I'm…

vhdl modelsim intel-fpga quartus

asked Apr 16 '15 at 18:20

Nate

26,164
34
130
214

votes

1 answer

verilog $readmemh takes too much time for 50x50 pixel rgb image

I am trying to compile a verilog code for FPGA programming where I will implement a VGA application. I use QuartusII and Altera. I am trying to use readmemh properly for acquiring a picture pixel by pixel. For now, I have converted a picture into…

verilog fpga system-verilog quartus

asked May 23 '15 at 22:55

ozgeneral

6,079
2
30
45

votes

3 answers

How to generate .rbf files in Altera Quartus?

What are .rbf files and how can i generate them from the Quartus output file .sof on windows ?

fpga intel-fpga quartus

asked Mar 01 '15 at 22:28

Eslam Medhat

votes

2 answers

Can't compile with VHDL 2008 Quartus Prime

I'm using Quartus Prime Lite Edition and I want to use unary operator nand on std_logic_vector like this library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity example1 is port( BIN : in std_logic_vector (7…

vhdl intel quartus

asked Apr 25 '21 at 12:07

Piotr Chmielewski

votes

1 answer

Quartus: Add dependencies from external file

I have lots of FPGA projects and some generic components shared among them. I’m searching for a way to add these components through an external file, so I can easily add new components to all my projects. I’ve moved all the set_global_assignment…

fpga quartus

asked Oct 18 '19 at 14:16

sebi707

votes

1 answer

How to assign pins in Quartus II

We are looking at moving some code into a CPLD or FPGA in order to make it faster. I have worked with Xilinks and their suite of tools before, but for some reason it was decided that we'd use Altera this time around so I am trying to get used to…

vhdl intel-fpga quartus

asked Apr 11 '11 at 11:46

shieldfoss

2 3

…

36 37 Next