Can't compile with VHDL 2008 Quartus Prime

Question

I'm using Quartus Prime Lite Edition and I want to use unary operator nand on std_logic_vector like this

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity example1 is
    port( 
        BIN : in std_logic_vector (7 downto 0);
        result : out std_logic
    );
end;

architecture Beh of example1 is
begin
    
    result <= nand BIN;
        
end Beh;

I tried to follow this instructions, changed VHDL version under VHDL Input in Compiler Settings. Still no effect and getting: Error (10500): VHDL syntax error at lab2.vhd(16) near text "nand"; expecting "(", or an identifier ("nand" is a reserved keyword), or unary operator

@busybee binary operators like this were added to VHDL 2008 to allow reduction of binary arrays. — Tricky, Apr 25 '21 at 14:57
@Piotr Chmielewski IIRC, Prime lite does not have full VHDL 2008 support, only prime pro does. Have you checked in the Quartus doocumentation that this feature is supported? Have you also checked that the file is specified or compiled as VHDL 2008? — Tricky, Apr 25 '21 at 14:59
Prime Lite no longer has VHDL 2008 support https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/po/ss-quartus-comparison.pdf — Tricky, Apr 26 '21 at 07:33

score 5 · Accepted Answer · answered May 17 '21 at 09:29

5

Quartus Prime Lite does not support VHDL 2008.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/po/ss-quartus-comparison.pdf

answered May 17 '21 at 09:29

Piotr Chmielewski

155
8

2

That's a dumb thing to charge for! – Russell Apr 29 '22 at 17:09

score 0 · Answer 2 · answered Apr 27 '21 at 20:26

This error is coming as "nand" requires two inputs.

From your question, it appears to me that you want to perform the bitwise nand operation on the input.

If yes, you can replace architecture as follows. I am assuming that you are familiar with the "generate for" syntax!

architecture Beh of example1 is 
--Signals for Storing Intermediate Bitwise Values
signal temp1:std_logic_vector(3 downto 0);
signal temp2:std_logic_vector(1 downto 0);

begin
-- First level of NAND Operations

label_1: for i in 0 to 3 generate
temp1(i)<=BIN(2*i) nand BIN(2*i+1);
end generate label_1;

-- Second level of NAND Operations

label_2: for j in 0 to 1 generate
temp2(j)<= temp1(2*j) nand temp1(2*j+1);
end generate label_2;

-- Getting the Final Output 

result<= temp2(1) nand temp2(0);
end Beh;

Thanks, Dr. Ray

Thanks for your reply! I saw that nand could be used with one vector only in 2008, so I asked how. Now I know that Quartus Prime Lite does not support it. — Piotr Chmielewski, May 17 '21 at 09:24

Can't compile with VHDL 2008 Quartus Prime

2 Answers2