5

I have the following VHDL code, its a entity of a project:

library ieee;
use ieee.std_logic_1164.all;
library work;
use work.typedef.all;

entity uc is
    port(faaaa: in std_logic_vector(15 downto 0);
          phi: in std_logic;
          isDirect,isRam,jmp,store,NarOut,arpOut:out std_logic);
    end entity uc;

architecture b8 of ua is
    signal   instt : std_logic_vector(15 downto 0);
    signal bit7: std_logic;
        begin
            bit7<='0';
            instt <= faaaa;
            ....
            process(phi) is
            ....
            end process;
end architecture b8;

The error says that:

object "faaaa" is used but not declared

What am I doing wrong here?

Qiu
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walidsarkis
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  • This error message is specific to a synthesis/simulation tool. Can you please add it's name as a tag so others can search for this message. – Paebbels May 29 '15 at 09:01
  • @Paebbels, it's a Quartus message [ID: 10482](http://quartushelp.altera.com/14.0/mergedProjects/msgs/msgs/evrfx_vhdl_is_not_declared.htm). Somewhere there's been analyzed an entity `uc` that doesn't have the declaration of `faaaa` found in architecture uc(b8). The entity `ua` with the declaration isn't being used in the architecture shown. –  May 29 '15 at 10:42

1 Answers1

7

Your entity is called uc, but the architecture b8 is of ua.

scary_jeff
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    ... which means that `faaaa` is declared somewhere else, and not visible inside this architecture. –  May 29 '15 at 08:58