This simple test leads to an error while compiling with modelsim whereas Quartus is fine to go through the whole synthesis/fitter process.
library ieee;
use ieee.std_logic_1164.all;
entity submodule is
port(
four_bits_input : in std_logic_vector(3 downto 0);
four_bits_output : out std_logic_vector(3 downto 0)
);
end entity;
architecture behav of submodule is
begin
four_bits_output <= four_bits_input;
end architecture;
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity globally_static_test is
port (
one_bits_input : in std_logic;
three_bits_input : in std_logic_vector(2 downto 0);
four_bits_output : out std_logic_vector(3 downto 0)
);
end entity;
architecture behav of globally_static_test is
begin
submodule_inst : entity work.submodule
port map(
four_bits_input => one_bits_input & three_bits_input -- Modelsim Error is here.
,four_bits_output => four_bits_output
);
end architecture;
Modelsim error is the well known :
(vcom-1436) Actual expression (infix expression) of formal "four_bits_input" is not globally static.
I have seen this type of affectation in wrapper a lot in different companies and on several projects.
My question is : "Who is actually right ? Modelsim or Quartus".
Edit :
I've first made the test with the following versions
- Modelsim v10.5b Intel FPGA Starter Edition - VHDL 2002
- Quartus Prime 17.1 - VHDL 1993
Then I changed the Modelsim compilation option to use VHDL 2008 and the error is gone.
