10

I've looked at all the previous questions and no one seems to have a problem as simple as mine. Also I've searched the web and can't find a solution.

I'm new to VHDL and am trying to compile the simple example provided by Altera, which is as follows:

library ieee;
use ieee.std_logic_1164.all;

entity light is
port(x1, x2: in std_logic;
          f: out std_logic);
end light;

architecture LogicFunction of light is
begin
    f <= (x1 and not x2) or (not x1  and x2);
end LogicFunction;

I followed the project creation steps in the Altera tutorial, but when I try to compile the project I get the error:

Error (12007): Top-level design entity "alt_ex_1" is undefined
Henke
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unplugngo
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    The link to the **Altera tutorial** is broken. It seems to be [the same tutorial as this one](ftp://ftp.intel.com/pub/fpgaup/pub/Intel_Material/9.0/Tutorials/VHDL/Quartus_II_Introduction.pdf). – Henke Mar 29 '21 at 15:35
  • The term `design entity` found in the error message is defined in the VHDL standard (e.g. IEEE Std 1076-2008 3. Design entities and configurations, 3.1 General) and the meaning of top-level. "The *design entity* is the primary hardware abstraction in VHDL. It represents a portion of a hardware design that has well-defined inputs and outputs and performs a well-defined function. A design entity may represent an entire system, a subsystem, a board, a chip, a macro-cell, a logic gate, or any level of abstraction in-between." –  Mar 31 '21 at 15:09
  • "... The top-level block in such a hierarchy is the design entity itself; such a block is an external block that resides in a library and may be used as a component of other designs. ..." It helps to understand "Elaboration of a design hierarchy defined by a design entity consists of the elaboration of the block statement equivalent to the external block defined by the design entity." (14.2 Elaboration of a design hierarchy). The net effect here is that the top-level design entity name is `light` and not `alt_ex_1`. You've made a typographical tool error. –  Mar 31 '21 at 15:18
  • An up-to-date link to the *Altera tutorial*, written out explicitly: [ftp://ftp.intel.com/pub/fpgaup/pub/Intel_Material/9.0/Tutorials/VHDL/Quartus_II_Introduction.pdf](ftp://ftp.intel.com/pub/fpgaup/pub/Intel_Material/9.0/Tutorials/VHDL/Quartus_II_Introduction.pdf). – Henke Apr 03 '21 at 13:42

5 Answers5

18

My problem was about verilog code compiler. But when I search for problem, I always saw this question. So I decided to add my solution too to guide others. It took me much time to find solution. here is what I had done to solve the problem.Just follow these steps (Quartus II 14.0.0) ; Assignments -> Settings -> Top-Level Entity ->Select your module

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Sabri Meviş
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13

In chapter Starting a New Project, you were asked to call your project light. It seems to me that you didn't follow that step correctly and name your project alt_ex_1. That's why you're getting 12007 error, since the compiler has no idea what is the top-level entity in you design.

To solve that problem you can:

  1. Change the top-level entity assignment in Assignments -> Device -> General.
  2. Set your module as top-entity via Project Navigator (Files -> Set as top-level entity).

Btw 1, 2, 3, ... - all about the same problem.

Qiu
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  • Many thanks, I didn't fully understand the meaning of top level entity in this instance. I assumed that because I only have one file that the software would assume the first entity. I notice that I can still call my project anything I like e.g 'alt_ex_3' but I must specify the top-level design entity as 'light'. Thanks again for your time. – unplugngo Sep 15 '14 at 06:50
2

Just put the pointer over the file name in the project navigator panel and click with right button and then push on (set as top-level entity). Done.

Hender
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1

A Short Answer

Error (12007): Top-level design entity "alt_ex_1" is undefined

The error message is far from trivial to make sense of, but in a roundabout way it does tell what is wrong. You are (probably) using alt_ex_1.vhd as the name of your design file.
In Altera Quartus, the file name must be the same as the name of the (top level) entity declared in the VHDL design code.
What you need to do is to change the file name from alt_ex_1.vhd to light.vhd.
To keep it simple, create a new project named light instead of alt_ex_1.

An Elaborated Answer

Reproducing the error is straightforward. Here is what I did. 1

After starting the Quartus Prime Lite Edition click File > New Project Wizard....
If you see an Introduction, click Next >. Choose a working directory.
As name of the project enter alt_ex_1. Click Next > twice and then Finish.
Create a design file: File > New....
Under Design Files, choose VHDL File, then OK.
Next File > Save As.... Type or paste alt_ex_1.vhd and click Save.
Paste the code:

library ieee;
use ieee.std_logic_1164.all;

entity light is
port(x1, x2: in std_logic;
          f: out std_logic);
end light;

architecture LogicFunction of light is
begin
    f <= (x1 and not x2) or (not x1  and x2);
end LogicFunction;

and save the file again.

Compile with Processing > Start > Start Analysis & Synthesis - or press Ctrl + K. The Message window displays the error:

12007 Top-level design entity "alt_ex_1" is undefined

To get rid of the annoying error, delete all the files that were created in the working directory, and then start all over. Follow the instructions as above, but this time make sure to replace every occurrence of alt_ex_1 with light.

In the Message window expect to see something like:

Quartus Analysis & Synthesis was successful. 0 errors, 1 warning

as one of the last lines.

1 Using Altera / Intel Quartus Lite 18.1 on Windows 10, but the version is likely not important.

References:

Henke
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0

The name of the .vhd file should be the same as the name of top-level entity, solution is simple - just replace light with alt_ex_1

Tladi Lebohang
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