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I have been trying to declare my type in a separate "mytypes.vhd" file as follows:

library ieee;
use ieee.std_logic_1164.all;

package mytypes is 
   type my_bus_array_type is array (0 to 3) of std_logic_vector(7 downto 0);
end package mytypes;

and then define an entity as follows:

library ieee;
use ieee.std_logic_1164.all;

library work;
use work.mytypes.all; 

entity my_entity is
   port(
      bus_array : in my_bus_array_type;
      ...
   );
end my_entity;

Well, this is not working. When I try to add the component to my library with the Altera Qsys tool, I get the following error:

Error: Verilog HDL or VHDL XML Interface error at my_entity.vhd(41): port "bus_array" has an unsupported type File: /home/project/my_entity.vhd Line: 41

Please note that the problem is the fact that I am trying to define inside an entity an array of standard_logic_vector, i.e. a multidimensional array. This code works correctly if I define an array of std_logic instead.

Qiu
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kean
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  • First comment : the port declaration should be `name : direction type` and **not** `type : direction name` – wap26 Jun 04 '12 at 12:48
  • Once you've fixed this, can you mention what is your compiler (and the compilation options) and what is its error message? – wap26 Jun 04 '12 at 12:49
  • done. I am quite new with HDL and quartus and I don't know exactly what the compilation options are... I didn't change any of them anyway, so I am compiling with the default options. – kean Jun 04 '12 at 13:11
  • Have you properly included the file with the `mytypes` package in your project? – wap26 Jun 05 '12 at 08:19
  • which version of quartus are you using? 10.x is a waste of time, use 11.2 ... – BennyBarns Sep 06 '12 at 08:06

5 Answers5

1

You mentioned you're using Quartus, which can be picky about using std_logic_vectors as base types for other items.

I do what I think you're after in Quartus using subtypes:

mytypes.vhd file:

library ieee;
use ieee.std_logic_1164.all;

package mytypes is 
  subtype BYTE_T            is std_logic_vector(7 downto 0);
  type    BYTE_A            is array (natural range <>) of BYTE_T;
  type    my_bus_array_type is array (0 to 3) of BYTE_T;
end package mytypes;

my_entity.vhd file:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.mytypes.all

entity my_entity is
port ( 
  my_bus_array1 : in BYTE_A(0 to 3);
  my_bus_array2 : in my_bus_array_type;
  ...

It's up to you whether you want to define the array range in the entity (perhaps using a generic), or in your package.

Charles Steinkuehler
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  • Thanks Charles, but unfortunately also this method doesn't work. I receive the same error message. I am starting to think that VHDL doesn't allow having arrays in an entity declaration, which are not of simple std_logic or similar. Is that impossible? – kean Jun 05 '12 at 07:19
  • @KeanMariotti: VHDL allows it just fine. Quartus appears to be limiting you :( – Martin Thompson Jun 05 '12 at 10:43
  • The code is shown as all one block, but the package declarations should be in their own file. Make sure the package file is listed in the project files section of Quartus, and is the first file listed. I just verified the above code compiles in Quartus version 9.0, with both the BYTE_A array and my_bus_array_type working fine as top-level entity ports. – Charles Steinkuehler Jun 05 '12 at 12:07
  • Thank you. I created a separate test project and it works just fine. I did it before, but I obviously missed some detail. However I still get the error message when Qsys performs the compilation while I am trying to add the component to my library. I wish to point out that I included "mytypes.vhd" in the HDL files list of the component editor. I also put at the top of the list. I can successfully compile the component as long as no entity port is an array of std_logic_vector. – kean Jun 05 '12 at 12:54
  • I can't help you with Qsys...I have found the SOPC tools too limiting and use VHDL with packages and generics to custom configure multiple designs from the same code tree. I recommend digging through the Qsys documentation (or maybe asking Altera) to see if you can support custom port types in Qsys. Quartus can handle it just fine, but Qsys might not. – Charles Steinkuehler Jun 05 '12 at 14:19
0

I am not an expert in VHDL but I think you have to write your code like this :

I edited : try this instead : 

    package mytypes is 
     type my_bus_array_type is array (0 to 3) of std_logic_vector(7 downto 0);  
end package mytypes;

    entity my_entity is
    port ( my_bus_array : in my_bus_array_type; 
    ...);
    end my_entity
jlink
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  • that's exactly what I did, sorry about the incompleteness of my code, I corrected it. It doesn't work anyway, my_bus_array_type cannot be used in an entity definition. – kean Jun 04 '12 at 10:43
0

You have to tell the compiler to use the types you created in the mytypes package:

use work.mytypes.all

entity my_entity is
port ( my_bus_array : in my_bus_array_type;
...
Charles Steinkuehler
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  • I have done that too, but it doesn't work. Here the problem is the array of std_logic_vectors. I can correctly compile if I declare an array of std_logic, but it is not the case with an array of std_logic_vectors. – kean Jun 04 '12 at 11:56
  • I do this all the time in Quartus, but the synthesis tools can get picky sometimes. I create a subtype for the std_logic_vector, then an array type of those subtypes. I'll make a new answer with example code for this method. – Charles Steinkuehler Jun 05 '12 at 03:22
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I've had similar problems, and it has had to do with handling of VHDL libraries. All HDL components in Qsys will be assigned a VHDL library with the library name set to the name of the Qsys project. Packages must be accessed with library explicitly (work. in your case) and this can mess things up. That being said, usually using packages in Qsys components has worked fine for me (including accessing them with work.).

To see how Quartus assigns and compiles into libraries, check "Design units" tab in Quartus. It lists units in folders of libraries. However, I've seen that packages will not be listed here, for some reason. Also see the .qip file of your Qsys project, where you can see exactly how Quartus has assigned your HDL files into a library.

The fact that your problem doesn't appear when instantiating your code directly in the Quartus project, rather than as a Qsys component, hints of the library issue being the explanation for this.

I've only found two references on the Qsys library handling: http://www.alteraforum.com/forum/showthread.php?t=33605 http://www.alterawiki.com/wiki/New_Qsys_Issues (see section "Unavoidable design unit collisions")

(On a side note, I often use arrays of std_logic_vector in Qsys components and never experienced a problem with that.)

Carl
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0

What you're trying to really define is a 2D array as a port. Unfortunately, QSYS does NOT support 2D arrays. No standard Qsys interfaces support anything more than a 1 dimensional port array. Hence you'd have to break the array apart in your top level entity, export the individual ports as conduits, and then reassemble them at a higher level back into an array. This is unfortunate but true.

Skrell
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