A test bench or testing workbench is an (often virtual) environment used to verify the correctness or soundness of a design or model, for example, that of a software product.
Questions tagged [test-bench]
292 questions
12
votes
2 answers
What's the best way to tell if a bus contains a single x in Verilog?
I have a test bench that monitors a bus. Some of the signals (bits) within the bus can be 1'bx. For a variety of reasons, I need to know if any of the signals within the bus are 1'bx. What's the best way to test (not for synthesis -- only for…
Doov
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5
votes
1 answer
Running multiple testbenches for VHDL designs
Whenever I create a VHDL design I tend to have many modules. Each of these modules are then connected to one main file and so everything is synthesised. But I want to write seperate test benches for each of these modules and one for the global…
Cheiron
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5
votes
1 answer
Accessing inputs and outputs in sub-modules from testbench
My device-under-test (DUT) has many sub-modules and I would like to test some of them.
My test fixture will be the top level of my project - one level higher than the DUT - and since I can only seem to access the inputs and outputs of the modules…
DevGoldm
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4
votes
1 answer
VHDL-2008 continuously force an external name
I'd like to be able to continuously force a signal down in my testbench hierarchy. Here is a simple example illustrating how I've been doing this in my test benches.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity…
Michael Grover
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4
votes
1 answer
How to select an element from a ComboBox menu using Vaadin Testbench?
I am doing some integration tests with vaadin version 7.6.4 and Testbench (4.0.3).
I have a view with several comboboxes. One of them has this property comboBox.setTextInputAllowed(false); For testing purposes, I want to change the default value on…
a-llorens
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4
votes
1 answer
'Illegal output or inout port' error when trying to simulate counter
I am new to verilog HDL and I have zero experience in digital circuit.
I learned one or two things off the internet and now I am trying to write
a test bench script for a counter script. I've obtained counter script from following…
user3655233
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3
votes
1 answer
How to use Arithmetic expression in Enum in system verilog?
`define REG_WIDTH 48
`define FIELD_WIDTH 32
typedef enum bit [`REG_WIDTH-1:0]
{
BIN_MIN = 'h0,
BIN_MID = BIN_MIN + `REG_WIDTH'(((1<<`FIELD_WIDTH)+2)/3),
BIN_MAX = BIN_MID + `REG_WIDTH'(((1<<`FIELD_WIDTH)+2)/3),
}reg_cover;
In…
Rishi Jaiswal
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3
votes
2 answers
Chisel test - internal signals
I would like to test my code, so I'm doing a testbench. I wanted to know if it was possible to check the internal signals -like the value of the state register in this example- or if the peek was available only for the I/O
class…
user54517
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3
votes
4 answers
vhdl modelsim return "1" or "0" status to command line
I am trying to create a self-testing VHDL testbench in which I need to true or false status (1 or 0) to the command line/shell that is calling the vsim commands to convey the overall pass/fail status of the testbench.
My simulator tool is modelsim.…
user2913869
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3
votes
3 answers
VHDL testbench for a device that uses two previously defined and tested entities
Warning: this is going to be long. Sorry if it's too verbose.
I'm just starting out on learning FPGAs and VHDL using Quartus Prime. Over the past few days I've taught myself:
How to write VHDL
How to make a component
How to write a testbench
How…
DiBosco
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3
votes
1 answer
VHDL state machine testbench - works when on board but not on simulation
I have the VHDL implementation that works on board, it detects the sequence 01110 and will raise a flag for 2 clock counts. It detects overlapping sequences as well where 011101110 would raise the flag twice.
I've checked my implementation with a…
Jack Yeoh
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3
votes
2 answers
VHDL Aggregate Assignment Using Aliases
I am having some trouble using aggregates in my VHDL test bench (short hand shown below).
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all
entity TB is
end entity;
architecture RTL of TB is
-- constant(s)
constant …
bgarisn
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3
votes
2 answers
How to install co-simulation support for myHDL
I am trying to setup myHDL with Python2 on Windows 10 in order to work with VHDL/Verilog testbenches using Python for the source code. The corresponding instructions can be found here.
I have successfully installed python, pip and then myHDL on my…
Abhishek Agarwal
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3
votes
1 answer
Delay a signal in VHDL Testbench
I would like to put a delay on a signal in my testbench. The problem is that I need hundreds of clock cycles and thus I don't want to use hundreds of intermediate signals.
Since this is just for a simulation use, is there any way to add a delay with…
A. Kieffer
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2
votes
2 answers
Why does the force statement get stuck? And how to force a single bit in an array of bits?
module dut_top;
wire [31:0] ctrl_32bit;
wire ctrl_1bit;
assign ctrl_32bit = 0;
assign ctrl_1bit=0;
initial begin #1000ns; end
endmodule
program automatic test;
initial begin
repeat(5) begin
…
Jack
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