Chisel test - internal signals

Question

I would like to test my code, so I'm doing a testbench. I wanted to know if it was possible to check the internal signals -like the value of the state register in this example- or if the peek was available only for the I/O

class MatrixMultiplier(matrixSize : UInt, cellSize : Int) extends Module {
  val io = IO(new Bundle {
    val writeEnable = Input(Bool())
    val bufferSel = Input(Bool())
    val writeAddress = Input(UInt(14.W)) //(matrixSize * matrixSize)
    val writeData = Input(SInt(cellSize.W))
    val readEnable = Input(Bool())
    val readAddress = Input(UInt(14.W)) //(matrixSize * matrixSize)
    val readReady = Output(Bool())
    val readData = Output(SInt((2 * cellSize).W))
  })

  val s_idle :: s_writeMemA :: s_writeMemB :: s_multiplier :: s_ready :: s_readResult :: Nil = Enum(6)
  val state = RegInit(s_idle)
...

and for the testbench :

class MatrixUnitTester(matrixMultiplier: MatrixMultiplier) extends PeekPokeTester(matrixMultiplier) { //(5.asUInt(), 32.asSInt())

    println("State is: " + peek(matrixMultiplier.state).toString) // is it possible to have access to state ?
    poke(matrixMultiplier.io.writeEnable, true.B)
    poke(matrixMultiplier.io.bufferSel, false.B)
    step(1)
...

EDIT : Ok, with VCD + GTKWave it is possible to graphically see these variables ;)

It sounds like you found the information you wanted. If so, consider accepting an existing answer or writing and accepting one yourself so others know the question has an answer. — Scott McPeak, Feb 21 '20 at 21:29

score 2 · Accepted Answer · answered Dec 11 '19 at 18:36

2

Good question. There's several parts to this answer

The Chisel supplied unit testing frameworks older chisel-testers and the newer chiseltest. Do not provide a mechanism to look into the wires directly. Currently the chisel team is looking into ways of doing that.
Both provide indirect ways of doing it. Writing VCD output and using printf to see internal values
The Treadle firrtl simulator, which can directly simulate a firrtl (the direct output of the Chisel compiler) does allow for peek, and poking any signal directly. There are lots of examples of how its use in Treadle's unit tests. Treadle also provides a REPL shell which can be useful for exploring a circuit with manual peeks and pokes

answered Dec 11 '19 at 18:36

Chick Markley

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So according with your second point, I should be able to see content of my `state` register. I don't know about writing VCD output, do you know where I can get some extra information about that ? Because my current `println` (second line of the test file) is generating an error :/ – user54517 Dec 11 '19 at 19:58
1

Take a look at https://github.com/freechipsproject/chisel-testers/wiki/Frequently-Asked-Questions for information about VCD. I am not sure about `println`, but it might be that you meant to use `printf`. `printf`s display its information during simulations. `println` displays *only* during the elaboration or compile phases of your test. – Chick Markley Dec 11 '19 at 22:15
1

Yeah even with the `printf` I got `java.util.NoSuchElementException: key not found: UInt<3>` and same when I try to display any non I/O signal. So if I understand, I should see the result of my `printf` if I edit my test to generate the VCD file as shown in the link, right ? – user54517 Dec 11 '19 at 22:39
printf and vcd should be completely independent. Can you post the line where this errors is occurring, it sounds like some other problem – Chick Markley Dec 12 '19 at 21:23
That's okay, thanks to VCD + GTKWave I have access to all of my registers visually, and I now use that to debug ;) Thanks ! – user54517 Dec 12 '19 at 21:25

score 0 · Answer 2 · answered May 18 '22 at 15:54

The older chiseltesters (io-testers) and current chiseltest frameworks allow debugging the signal values with .peek() function that works well for the interface signals.

I haven't found a way to peek() an internal signal while debugging a testcase. However, Treadle simulator can dump the values of internal signals when it is running in verbose mode:

Add the annotation treadle.VerboseAnnotation to the test:

  `test(new DecoupledGcd(16)).withAnnotations(Seq(WriteVcdAnnotation, treadle.VerboseAnnotation))`

When debugging in the IDEA and the test stops at breakpoint, the changes in the values of all internal signals up to this point are dumped to the Console.

This example will also generate the VCD wave file for further debugging.

Chisel test - internal signals

2 Answers2