A package for using Python as a hardware description and verification language. Although it cannot be synthesized directly into hardware, MyHDL code can be automatically translated to Verilog or VHDL, and synthesized with existing HDL development tools.
Questions tagged [myhdl]
34 questions
11
votes
1 answer
Python ast package: traversing object hierarchies
The following is a Python code snippet using the ast and symtable
packages. I am trying to parse the code and check the types. But I
don't understand how to traverse objects to get to the actual variable
being referenced.
The following code…
Christopher Felton
- 420
- 4
- 11
6
votes
3 answers
Difference between yield statement in python and MyHDL
I am currently learning MyHDL for my summer project.
I have a problem grasping the functioning of yield statement in it. Though its true that the MyHDL is based upon python, it uses its yield statement in a specialized way.
the link for the same is…
Adwaitvedant
- 253
- 3
- 10
5
votes
5 answers
Better platform to turn software into VHDL/Verilog for an FPGA
I am looking at developing on an FPGA, but it would be easier for me to write the code in Python or Scala and have it converted to VHDL or Verilog.
I want to have many sensors hooked up to a device, and as the data comes in, calculations are done…
James Black
- 41,583
- 10
- 86
- 166
4
votes
1 answer
How to implement interfaces in MyHDL
In VHDL, I often use records to group related signals into something that can be passed around as a single object, e.g. in a port map. What's the MyHDL way of doing this?
geschema
- 2,464
- 4
- 30
- 41
3
votes
2 answers
How to install co-simulation support for myHDL
I am trying to setup myHDL with Python2 on Windows 10 in order to work with VHDL/Verilog testbenches using Python for the source code. The corresponding instructions can be found here.
I have successfully installed python, pip and then myHDL on my…
Abhishek Agarwal
- 1,190
- 2
- 19
- 38
2
votes
1 answer
How to receive an input bus in MyHDL?
I'm trying to learn MyHDL and for that I was trying to create a very simple artificial neuron that could later be used in a simple artificial neural network.
First I designed an artificial neuron that could only handle a single input and weight…
Mira
- 1,983
- 1
- 11
- 10
2
votes
2 answers
How to assign a value to a sliced output signal?
I'm a beginner with myhdl.
I try to translate the following Verilog code to MyHDL:
module ModuleA(data_in, data_out, clk);
input data_in;
output reg data_out;
input clk;
always @(posedge clk) begin
data_out <= data_in;
…
killruana
- 158
- 6
2
votes
2 answers
MyHDL: Can't translating Signal.intbv.max to VHDL
I'm new to python and MyHDL so I started by converting old VHDL projects to MyHDL. This project is a vga timer that can accept any width, height, and frequency (given that they actually work with monitors). It doesn't successfully convert to either…
Nathan Sketch
- 21
- 1
- 4
2
votes
1 answer
Module Instantiation in myhdl
I'm currently looking into myHdl to see if it's worth using or not. However, I've come across a hiccup regarding the instantiation of modules. I've got two files, one that's a module and one that's the testbench. Inside the testbench, I've…
Jpwang
- 143
- 1
- 12
2
votes
1 answer
Unable to display the simulation with EDAPlayground compiler
I have tried the following code from myHDL manual on EDAPlayground.com, but it didn't print anything out for me. Can anyone show me why ? and how to solve this ?
My configuration on the site is outlined here.
Testbench+Design : Python…
user3663339
- 33
- 2
2
votes
1 answer
MyHDL: library use clauses in user-defined code
Is there a way to specify library use clauses when using MyHDL user-defined code?
Consider the following example, which models a differential buffer that is available in the Xilinx unisim library:
from myhdl import *
def ibufds(I, IB, O):
"""…
geschema
- 2,464
- 4
- 30
- 41
2
votes
1 answer
Connect internal signal to output port in MyHDL module
Considering the following example (a simple 8-bit counter), is there a simpler way to connect the internal s_count signal to the o_count port?
def counter(i_clk, i_reset, o_count):
""" A free-running 8-bit counter with a synchronous reset…
geschema
- 2,464
- 4
- 30
- 41
1
vote
1 answer
MyHDL Signals inside functions not showing up in VCD
Should I be able to see these in the generated VCD file?
@always(clk.posedge)
def MentorCluster():
j = Signal(0)
mentorq0, mentorq1, mentorq2, mentorq3 = [[Signal(0) for j in range(10)] for i in range(4)]
I can see all the…
user3761340
- 603
- 5
- 19
1
vote
1 answer
Myhdl: assigning a bitslice to a signed variable fails with negative values
The code added fails with a ValueError and i have no idea whats going wrong. Here is what i want to do:
In my fpga i receive data via spi.
Data is a bipolar signal (in the sense of a measurement signal) arriving in a 16 bit register rxdata.
the task…
Stefan Karrer
- 11
- 3
1
vote
2 answers
myhdl cosimulation test fail
I am trying to download myhld on ubuntu and also install the cosimulation. myhdl was installed fine but when following the cosimulation installation i am unable to properly run the test case provided within the download package. an error is coming…
gauravr
- 11
- 2