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Questions tagged [edaplayground]

EDA playground allows the simulation of SystemVerilog, Verilog, VHDL, C++/SystemC and other HDLs in a web browser. The goal is to help the learning of design/testbench development and easier code sharing (particularly on sites like Stack Overflow).

The link to the site is: EDA playground

Use this tag for questions about writing and simulating Hardware Description Languages (HDL) on EDA playground.

Help on using the site is also available in the Forum.

28 questions
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How to compile and run a verilog program which calls C function?

I am not trying to use a DPI call, but a simple Verilog program which internally uses its PLI to call a function written in C language. I don't know about static linking. I am using edaplayground. Can anyone tell me which simulator should I use and…
user1978273
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Using typedef with wire in SystemVerilog

When using typedef to declare a user-defined type, both these forms are accepted by EDA Playground: typedef reg[4:0] reg5; typedef logic[4:0] logic5; However, if doing something similar based on wire type, then this format fails: typedef wire[4:0]…
Taher Anaya
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3
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1 answer

Using Systemverilog to read then print binary file. First bytes read & print ok, trouble\w byte containing a 1 in the ms bit position encountered

The Systemverilog code below is a single file testbench which reads a binary file into a memory using $fread then prints the memory contents. The binary file is 16 bytes and a view of it is included below (this is what I expect the Systemverilog…
Mikef
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Issue with reading bus signal. Compare to my Modelsim DE 10.2c and 10.4. EDAplayground Modelsim 10.1d has different result

Hi any SystemVerilog experts with Mentor Graphic Modelsim Tool. I am writing a monitor task to process a simple PCI single word write/read bus event. Somehow EDAplayground Altera Modelsim 10.1d requires extra clock cycle for unknown reason while…
Michael Li
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2
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1 answer

Verilog testbench error multiplex 4x1 using EDAPlayground

I'm doing a Multiplex 4x1 in Verilog using EDAPlayground, but I still get testbench errors, and I don't know why. Here is one error: ERROR VCP2000 "Syntax error. Unexpected token: and[_AND]." "design.sv" 26 6 module mux4x1( input x1, x2, x3,…
Connor
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1 answer

EDAplayground error: Execution interrupted or reached maximum runtime

It has some error in my code, but I can't find anything wrong with my code. EDA Playground says: Execution interrupted or reached maximum runtime. Here is my code: forever #5 clk = ~clk;
full_adder0
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Clock waveform does not show in EDAplayground

When trying to get the Clock waveform to display in EDA Playground I get the error Execution interrupted or reached maximum runtime. How do I get the wave form to show? Code on EDA Playground: module test; reg clk; initial begin …
Abhi
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2
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1 answer

Unable to display the simulation with EDAPlayground compiler

I have tried the following code from myHDL manual on EDAPlayground.com, but it didn't print anything out for me. Can anyone show me why ? and how to solve this ? My configuration on the site is outlined here. Testbench+Design : Python…
user3663339
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1 answer

EDA playground ERROR VCP5294 "Undefined package uvm_pkg"

I'm trying to compile a small UVM verification environment in EDA playground. I'm getting this error: EDA playground ERROR VCP5294 "Undefined package uvm_pkg. The code attached below: import uvm_pkg::*; `include "reg_pkg.sv" module testbench; …
Ayala
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1 answer

Warning: Only a single slice of data found. Did you specify valid 'From/To' times?

I've typed a design code and a testbench code for inverter circuit. The input is of 4 bits, and so is the output. I've tried to display the waveform using: $dumpfile("dump.vcd"); $dumpvars(1); However, it keeps giving me the message: Warning:…
Mariam Atef
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2 answers

Error by VCS tool on uvm_hdl_deposit usage on edaplayground

I am trying to execute code @ https://www.edaplayground.com/x/e2Pe. The code seems to be error free. However, when trying to simulate with VCS tool, it is giving me below error: UVM_ERROR: set: unable to write to hdl path…
supal
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EDA Playground EPWave $dumpfile error: no vcd file found

I am trying to simulate my design in EDA Playground. I tested my design file and testbench file in my local computer using ModelSim (not from EDA), and it was successful. However, I tried to do the same with EDA Playground. It is successfully…
efe373
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EDA Playground $dumpfile: No *.vcd file found

I am having trouble getting some code to run in EDA Playground. I keep getting the message: No *.vcd file found. EPWave will not open. Did you use '$dumpfile("dump.vcd"); $dumpvars;'? But, I have it included in the code. Here's the…
user13442501
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2 answers

Verilog race with clock divider using flops

I made a basic example on eda playground of the issue I got. Let s say I have two clocks 1x and 2x. 2x is divided from 1x using flop divider. I have two registers a and b. a is clocked on 1x, b is clocked in 2x. b is sampling value of a. When we…
Viktorinox
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Facing errors while running VHDL code using EDA playground

I'm trying to run the following VHDL code using EDA playground as no VHDL simulator is installed on my Laptop. The upper part is the source code and lower part is the testbench. However, getting some errors which need to be resolved. The errors are…
Abdullah Al Mamun
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