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Questions tagged [questasim]

Mentor Graphics software to perform a functional simulation of a VHDL or Verilog HDL designs

Mentor Graphics software to perform a functional simulation of a VHDL or Verilog HDL designs

90 questions
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2 answers

vsim does not accept -modelsimini parameter on Windows

I'm using the command line argument -modelsimini to specify my own modelsim.ini file for most QuestaSim / ModelSim executables. This works perfectly fine on Linux for vcom and vsim, as well as for vcom on Windows. But the Windows vsim…
Paebbels
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2 answers

Why should an HDL simulation (from source code) have access to the simulator's API?

This is a question inspired by this question and answer pair: call questa sim commands from SystemVerilog test bench The questions asks how Verilog code could control the executing simulator (QuestaSim). I saw similar questions and approaches for…
Paebbels
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6
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1 answer

Finding when a certain signal has a particular value in Modelsim using tcl

I'm trying to speed up debugging. In a large trace I'm search for particular values of a signal. Im using QuestaSim 10.0b under linux. I already found out that can be done in Modelsim/QuestaSim with the following command searchlog -expr { stream ==…
sebs
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How to bind a SV interface signal to a VHDL type?

I am trying to bind an interface to my VHDL module. The signal that I want to bind to is defined as follows in the module: TYPE dut_fsm_type is ( IDLE_STATE, WAIT_STATE, …
noobuntu
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3
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2 answers

Why has this concurrent statement less than 100% code coverage?

Why has the following clock generation statement not 100% code coverage in ModelSim/QuestaSim? clk <= not clk after 5 ns when not finished; This is the full example: library ieee; use ieee.std_logic_1164.all; entity coverage1_tb is end…
Paebbels
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1 answer

What is the meaning of numbers in UVM_INFO?

The following message is from a transcript file created by running QuestaSim to simulate dut. What does the number 39 mean? UVM_INFO /home/Icer/nocc/noc-router/vips/hermes_pkg/src/hermes_agent.sv(39) @ 0: uvm_test_top.env.agent_master_0…
benjstark
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Warning "Range choice direction does not determine aggregate index range direction" when compiling VHDL with QuestaSim

I am getting a warning which I do not understand when compiling VHDL in QuestaSim: (vcom-1514) Range choice direction (downto) does not determine aggregate index range direction (to). The code which triggers the warning is similar to having signal…
njg
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1 answer

VHDL-2008 external names: reference verilog net?

Is it possible to use VHDL-2008 hierarchical references / external names to reference Verilog nets? Questa Sim (10.6c) stops the simulation with this error message: vsim-8509: The object class "SIGNAL" of "dut_i.my_net" is different from the class…
user2436850
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2 answers

Overloading function in subprogram, but I it has "already been defined"

I'm trying to compile my subprogram pack and I get this error: ** Error: C:/Users/kmgrytte/Downloads/subprog_pck.vhd(16): (vcom-1295) Function "parity" has already been defined in this region. ** =====> Prior declaration of "parity" is at…
Katrine Grytten
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2 answers

Which SystemVerilog construct corresponds to VHDL string?

I'm trying to create a SystemVerilog module that I could connect to a VHDL string. However, I cannot find a corresponding type in SystemVerilog. Using type "string" results in elaboration error in Questa. VHDL code: library IEEE; use…
Andy
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How to pass an array type as generic type parameter to a VHDL package?

I'm working on a generic package (list) in VHDL-2008. This package has a type generic for the element type. If I declare an array type of this element type within the package, it's a new type. So for e.g. integer, my new integer_array would be…
Paebbels
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1 answer

How to write a makefile where the compiled object files are in a different directory with a different name?

So I'm trying to write a Makefile to use with QuestaSim and systemverilog files. If you don't know what that is (and most people won't) then don't worry, it's not that relevant to my problem. I have a project director containing: src/ work/…
Andrew Parlane
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Why can the argument of `uvm_info not be convert2string()?

I defined a class called repeat_seq, which extends from base_seq, which extends from uvm_sequence. Some slicing code has shown the following: class repeat_seq extends hermes_base_seq; ... hermes_router_seq_config cfg; ... task pre_body(); …
benjstark
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Module's parameter initialization troubles

I want to have universal function to initialize same module with different parameters. One of them is packed array with size depends on another parameter. I've tried something like this: package my_pkg; class helper #( parameter seed =…
Don Rumata
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SystemVerilog QuestaSim - Pass string to $fdumpvars to save multiple VCD files

I am trying to generate multiple VCD file inside the same initial begin in QuestaSim 2021.3 (latest). I found this section in the QuestaSim user manual: But, I am only able to pass a "/hardcoded/path/to/vcdfile.vcd" as filename, and this is true…
a_bet
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