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Is it possible to use VHDL-2008 hierarchical references / external names to reference Verilog nets? Questa Sim (10.6c) stops the simulation with this error message:

vsim-8509: The object class "SIGNAL" of "dut_i.my_net" is different from the class "net" of the denoted object.

Here's the VHDL code that fails:

alias my_alias is << signal dut_i.my_net : std_logic >>;
user2436850
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    This is outside of the scope of VHDL, as it cross language compatibility is not defined in the LRM. This is a tool dependent issue. How is my_net declared in the verilog? technically, everything in verilog is a variable (maybe try this instead of signal) For cross language access, you may be limited to using signalspy. – Tricky Jan 16 '19 at 10:21
  • In this case *my_net* is the output of a Verilog Module (that is left unconnected/open in the next hierarchy). Using 'variable' instead of 'signal' results in a similar error. – user2436850 Jan 16 '19 at 10:47
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    Then I suggest reading up on signal spy (other vendors also provide similar packages, but they are all proprietary). – Tricky Jan 16 '19 at 11:43

1 Answers1

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According to the Questa User Manual:

Questa SIM supports the IEEE 1076-2008 standard “external name” syntax that allows you to make hierarchical references from VHDL to VHDL. Currently, these references can cross Verilog boundaries, but they must begin and end in VHDL.

Thus, the answer is no.

Questa does provide a set of Signal Spy procedures to access your Verilog signals via string names. You must also turn on optimization visability to access these signals since the strings are not parsed until run-time.

dave_59
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  • 10.6d user manual, Chapter 10 Mixed-Language Simulation, Separate Compilers with Common Design Libraries, Using Hierarchical References. –  Jan 17 '19 at 19:48