Why has the following clock generation statement not 100% code coverage in ModelSim/QuestaSim?
clk <= not clk after 5 ns when not finished;
This is the full example:
library ieee;
use ieee.std_logic_1164.all;
entity coverage1_tb is
end entity;
architecture tb of coverage1_tb is
signal clk : std_logic := '1';
signal finished : boolean := false;
begin -- architecture tb
clk <= not clk after 10 ns when not finished;
--clk <= not clk after 10 ns when not finished else unaffected;
process
begin
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
finished <= true;
wait;
end process;
end architecture;
If I add this else branch: else unaffected
, then I get 100% coverage.
Concurrent signal assignment are translated into processes with sequential signal assignments (LRM 11.6). A unaffected branch is translated into a null statement (LRM 11.6, Note 2; LRM 10.5.2.1).
I'm not sure why ModelSim/QuestaSim demands me to write an explicit else branch, which contains no waveform.