I am trying to execute code @ https://www.edaplayground.com/x/e2Pe. The code seems to be error free. However, when trying to simulate with VCS tool, it is giving me below error:
UVM_ERROR: set: unable to write to hdl path (top.dut_inst.BOOT_MODE)
You may not have sufficient PLI/ACC capabilites enabled for that path
10 3.1 Force failed...
It looks like I need to set some options, but I am not aware. I tried giving +vpi +acc
, but that did not work out.
Here is the complete command:
vcs -licqueue '+vpi' '+pli' '+acc' '-timescale=1ns/1ns' '+vcs+flush+all' '+warn=all' '-sverilog' +incdir+$UVM_HOME/src $UVM_HOME/src/uvm.sv $UVM_HOME/src/dpi/uvm_dpi.cc -CFLAGS -DVCS design.sv testbench.sv && ./simv +vcs+lic+wait
Here is the relevant testbench code:
if(uvm_hdl_deposit("top.dut_inst.BOOT_MODE",4'b0000)) begin
$display($time,"\t1 Forced value...");
end else begin
$display($time,"\t3.1 Force failed...");
end