How to implement interfaces in MyHDL

Question

In VHDL, I often use records to group related signals into something that can be passed around as a single object, e.g. in a port map. What's the MyHDL way of doing this?

Christopher Felton · Accepted Answer · 2014-01-14T18:40:32.413

4

Interfaces are available in the 0.9-dev and are straightforward. If you have an object (class) with Signals in it it will be name extended in conversion.

It is explained in the MEP http://www.myhdl.org/doku.php/meps:mep-107

More examples available here (I realize it is not well documented - yet):

https://bitbucket.org/cfelton/minnesota

Also, a small example available here:

http://www.edaplayground.com/s/130/941

edited Jan 14 '14 at 18:40

answered Jan 14 '14 at 04:14

Christopher Felton

420
4
11

1

Fabulous. Let's get rid of these ugly signal lists ;-) – geschema Jan 14 '14 at 18:17
Beauty is in the eye of the beholder :) List of Signals is very useful for modeling memory (and convertible). – Christopher Felton Jan 14 '14 at 18:42

How to implement interfaces in MyHDL

1 Answers1