2

Is there a way to specify library use clauses when using MyHDL user-defined code?

Consider the following example, which models a differential buffer that is available in the Xilinx unisim library:

from myhdl import *

def ibufds(I, IB, O):
    """ Xilinx Differential Signaling Input Buffer"""
    @always_comb
    def output():
        O.next = I        
    return instances()

ibufds.vhdl_code = """    
IBUFDS_inst : IBUFDS
generic map (
    DIFF_TERM => FALSE,
    IBUF_LOW_PWR => TRUE,referenced I/O standards
    IOSTANDARD => "DEFAULT")
port map (
    O => O,
    I => I,
    IB => IB
);"""

Converting this module to VHDL code works fine, but what is missing is the following use clause in the header of the VHDL file:

library unisim;
use unisim.vcomponents.all;

How can I fix that?

geschema
  • 2,464
  • 4
  • 30
  • 41
  • On a note unrelated to your question, I would suggest you using $names (see [example](http://docs.myhdl.org/en/latest/manual/conversion_examples.html#conv-usage-custom)) inside your vhdl_code block to let myhdl put the correct names there. While your example might work in a simple case, once integrated in a bigger design, you will definitely need them. – Ben Jun 15 '14 at 10:38

1 Answers1

3

Yes, toVHDL() supports a use_clauses attribute. This can hold a (possibly multiline) string that will be inserted at the appropriate location. This is just inserted, so you can also add library declarations.

This is supported, but I noticed I forgot to add it to the documentation - needs to be fixed.

Currently, when using this attribute, the pck_myhdl* use declaration is omitted - I used use_clauses in projects where another name for that package was desired. This looks slightly confusing, perhaps it would be better to keep that functionality separate using a different parameter.

Jan Decaluwe
  • 2,405
  • 19
  • 18
  • 3
    It's hard to express how happy I am to find myHDL. As a serious Python programmer wanting to convert some algorithms to HDL, I wasn't relishing the learning curve to getting productive in VHDL or Verilog. I found myself thinking "surely Python could be made to represent the necessary logic, then I can just connect it to my python algorithms for testing and it can then write the HDL for me". Essentially, you have done exactly that. The one missing piece for me was how I integrate with existing libraries, which this question answers. Jan, I salute you - you have made me a happy pythonista. – Henry Gomersall May 21 '14 at 21:09