Questions tagged [ghdl]

GHDL is an open source and freely available implementation of a VHDL analyzer and simulator written by Tristan Gingold in Ada. There are several versions including a gcc compiler front end and a just in time direct compile mcode version commonly found on Windows PCs.

GHDL is capable of analyzing, elaborating and simulation VHDL source files compliant with the IEEE Std 1076-1993, and as a work in progress is being upgraded to -2008 compliance.

The tag's intended use is to decorate VHDL questions that require ghdl specific answers relating to tool use. See also vhdl.

GHDL is invoked via the command line, it's specific operation passed by command line parameter. Basic command flags include those for analysis, elaboration and running a VHDL design specification as well as specific functions for managing simulation libraries and building models.

For waveform display ghdl is used in conjunction with GTKWave an open source waveform display tool.

GHDL is distributed for Windows, Linux, FreeBSD and OS X platforms as is GTKWave.

124 questions

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4 answers

How do I compile and run a VHDL program on Mac with ghdl?

i just wrote a simple VHDL program. I saved the file as a .vhd file. Then I compiled it with ghdl -a test.vhd and then built and executable file with ghdl -e test And finally tried to run it with ghdl -r test What happened is that I now have a…

macos vhdl ghdl

asked Jun 12 '13 at 15:51

user2426316

7,131
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How to write an integer to stdout as hexadecimal in VHDL?

I can print an integer as decimal to stdout with: library std; use std.textio.all; entity min is end min; architecture behav of min is begin process is variable my_line : line; begin write(my_line, 16); …

vhdl ghdl

asked Jun 17 '16 at 11:02

Ciro Santilli OurBigBook.com

347,512
102
1,199
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3 answers

Modelsim and GHDL cannot dump vhdl user-defined signal types into vcd?

I'm trying to dump internal signals from a simulation executed either by modelsim or ghdl. Everything works fine using: For modelsim, add vhdl sources, and compile all then: vsim -novopt work.uut_testbench vcd file ../uut.vcd; vcd limit…

signals vhdl modelsim ghdl

asked Mar 11 '12 at 13:02

Tarek Eldeeb

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1 answer

"component instance "uut" is not bound" when simulating test bench with GHDL simulator

I am having a problem with using GHDL (http://ghdl.readthedocs.io/en/latest/) to simulate my VHDL design. So, when I use the command ghdl -e Averager_tb to compile the test bench with GHDL I get the warning: Averager_tb.VHD:33:3:warning: component…

vhdl fpga hdl ghdl

asked Jul 21 '16 at 11:18

SomeRandomPhysicist

1,531
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42

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1 answer

Running multiple testbenches for VHDL designs

Whenever I create a VHDL design I tend to have many modules. Each of these modules are then connected to one main file and so everything is synthesised. But I want to write seperate test benches for each of these modules and one for the global…

unit-testing vhdl verification ghdl test-bench

asked Jan 23 '16 at 23:10

Cheiron

3,620
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2 answers

Why doesn't llvm-config on Windows emit the correct parameters for clang++.exe?

I'm no experienced LLVM user, but I'm trying to compile a Linux LLVM project on Windows. The project is GHDL. Because ready-to-use LLVM installers for Windows don't have llvm-config bundled, I needed to compile LLVM and clange from sources. The…

windows llvm clang++ llvm-clang ghdl

asked Jan 08 '16 at 10:28

Paebbels

15,573
13
70
139

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2 answers

VHDL: Mealy FSM not producing state changes at clock edges?

I am fairly new to VHDL and am following this tutorial to implement the following Mealy Finite State Machine: and have written the following code in VHDL: library ieee; use ieee.std_logic_1164.all; entity fsm is port(clk, rst, in1 : in…

vhdl fsm ghdl

asked Oct 26 '22 at 14:06

First User

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2 answers

vhld 2008 libraries missing in ghdl installation

sudo apt-get install ghdl seems to install everything correctly, but no VHDL2008 libraries. How can I add these? /usr/bin/ghdl -i --std=08 --work=work /home/user/Projects/endian_swapper/tests/../hdl/endian_swapper.vhdl && \ /usr/bin/ghdl -m …

ghdl

asked Apr 14 '20 at 07:36

Marcus

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2 answers

VHDL Case choice is not locally static

This code works with some tools Aldec Riviera Pro but not others GHDL ( ERROR choice must be locally static expression) LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.numeric_std.ALL; ENTITY INSTRUCTION_PROCESSOR IS PORT ( clk…

vhdl ghdl

asked Feb 12 '20 at 12:58

Caspar

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3 answers

GHDL simulator doesn't support vhdl attributes without error?

I wrote some vivado RTL and then added some vhdl attributes to the ports of the entity to define the interface to Xilinx Vivado tool as follows: library ieee; use ieee.std_logic_1164.all; entity vivado_rtl_island is port( -- Clocks …

vhdl fpga xilinx vivado ghdl

asked Jun 04 '19 at 12:52

pico

1,660
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0 answers

VHDL simulation won't run

I have just picked up The Designer's Guide to VHDL and I am working through the exercises in the first chapter. I ran into an issue with my 2 bit multiplexer that I don't understand. The code for my multiplexer: library ieee; use…

vhdl ghdl

asked Nov 27 '18 at 19:27

Greg McWilliams

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1 answer

How can I initialize an array of length 1 in VHDL

I am desperately trying to assign a constant that is an array of length 1 in VHDL, but it doesn't seem to work (with GHDL), it complains that I can't assign a literal of the type which is inside the array, into the array. package test is …

arrays vhdl literals ghdl

asked Feb 10 '18 at 21:20

FSMaxB

2,280
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1 answer

How to include vhdl fixed point library to ghdl-0.33?

I am new to ghdl simulator,and using ghdl on windows. I have setup ghdl (ghdl-0.33-win32) on my computer and tried out simple adder code and it worked. I currently need to simulate some math equations where I have used David Bishop's fixed and…

floating-point vhdl simulation fixed-point ghdl

asked Aug 11 '17 at 20:54

komto909

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1 answer

Modify VHDL generic value with ghdl in cocotb

I managed to read generic module value with cocotb without problem. But if I can't manage to write it. My VHDL generic is : ... generic ( ... C_M00_AXI_BURST_LEN : integer := 16; ... ) I can read it in cocotb: …

python vhdl ghdl cocotb

asked May 18 '17 at 06:57

FabienM

3,421
23
45

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4 answers

Why does PowerShell chops message on stderr?

I'm using a PowerShell script to control different compilation steps of an compiler (ghdl.exe). The compiler has 3 different output formats: No output and no error => $LastExitCode = 0 outputs on stderr (warnings), but no errors => $LastExitCode =…

powershell error-handling ghdl

asked Nov 21 '15 at 01:19

Paebbels

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