How can I initialize an array of length 1 in VHDL

Question

I am desperately trying to assign a constant that is an array of length 1 in VHDL, but it doesn't seem to work (with GHDL), it complains that I can't assign a literal of the type which is inside the array, into the array.

package test is
    constant length : integer := 1; -- this could come from a different package

    type integer_array is array ((length - 1) downto 0) of integer;

    constant my_array : integer_array := (1);
end test;

When I try to compile this with GHDL I get the error message test.vhdl:8:46:error: can't match integer literal with type array type "integer_array"

If I change length to 2 though and use (1, 2) as literal, it works perfectly.

So how do I initialise an array of length 1?

@Paebbels I'm using ghdl 0.35, I don't actually know which standard it uses by default, but my code needs to be compatible with Xilinx Vivado, I should probably manually specify the standard in the future. — FSMaxB, Feb 10 '18 at 22:48
GHDL defaults to VHDL-93, you can specify the standard with option `std` => `--std=08`. You can and should enabled VHDL-2008 features in Vivado too. — Paebbels, Feb 10 '18 at 23:01
IEEE Std 1076-2008, 9.3.3 Aggregates, 9.3.3.1 General, *...Aggregates containing a single element association shall always be specified using named association in order to distinguish them from parenthesized expressions.* As a parenthesized expression it's of the wrong type and the revision of the standard isn't of concern here. — , Feb 11 '18 at 00:36
The restriction comes from the [Ada83 precursor to VHDL](http://archive.adaic.com/standards/83lrm/html/lrm-04-03.html) albeit with slightly different terminology - *Aggregates containing a single component association must always be given in named notation.* Well known to both VHDL and Ada communities, it's in the [VHDL FAQ](https://tams.informatik.uni-hamburg.de/vhdl/doc/faq/FAQ1.html#aggregates). — , Feb 11 '18 at 15:41
Named association is the answer. I'll add one point regarding gigabytes of source code : I've seen some HUGE auto-generated VHDL codes before. GHDL is available with three compiler back-ends : gcc, llvm and its own JIT compiler, mcode. A few years ago there were some experiments comparing gcc and mcode backends; gcc (because of its huge number of optimisation passes) struggled (swapping and eventually dying) to process GB sized VHDL codes which mcode simply breezed through. LLVM wasn't ready to be part of those tests, I'd expect it to be somewhere between these two. — , Feb 11 '18 at 18:06

score 3 · Answer 1 · answered Feb 10 '18 at 21:35

3

I found to ways to do it, both not quite ideal:

With explicit index

package test is
    constant length : integer := 1; -- this could come from a different package

    type integer_array is array ((length - 1) downto 0) of integer;

    constant my_array : integer_array := (0 => 1);
end test;

With `others`

package test is
    constant length : integer := 1; -- this could come from a different package

    type integer_array is array ((length - 1) downto 0) of integer;

    constant my_array : integer_array := (1, others => 0);
end test;

Although I still hope that there is a better way.

answered Feb 10 '18 at 21:35

FSMaxB

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AFAIK there is no other way. And why is this not ideal? – JHBonarius Feb 11 '18 at 10:01
@JHBonarius Because I'm autogenerating VHDL and this means that I need a special case if the array happens to have a length of 1. (I don't want to use explicit indices all the way, because the VHDL that I generate can get up to several gigabytes and every character counts). But I already implemented the special case, since there is no way around it. – FSMaxB Feb 11 '18 at 10:05
**GIGABYTES** of vhdl code? Are you serious?? Considering the code is plain text... I've never heard of something like that before. And I've seen some very big designs in my career. I cannot image simulation or synthesis tools could handle that. You would need hundereds of GB RAM... And weeks to process. – JHBonarius Feb 11 '18 at 10:34
@JHBonarius: Vivado can handle it and the machine I'm running it on has enough RAM (not TB's). And it's just a huge junk of data as constants in the form of arrays of records. These are then looped over to generate the actual design. The reason it is so much code is because the Syntax is so verbose. – FSMaxB Feb 11 '18 at 10:37
wouldn't it be better to read the constants from a file/files? You're allowed to initialize RAMs etc. from files in synthesis. – JHBonarius Feb 11 '18 at 10:39
@JHBonarius: That's actually a good idea if the current approach hits its limits. Although this would require me to write a parser in VHDL, and VHDL isn't the best general purpose programming language in the world. (and a simple CSV is not enough in my case). But I'll keep that approach in mind, thanks. – FSMaxB Feb 11 '18 at 10:42
1

The LRM (section 9.3.3 Aggregates) states: "Aggregates containing a single element association shall always be specified using named association in order to distinguish them from parenthesized expressions." https://stackoverflow.com/questions/35359413/2d-unconstrained-nx1-array/35362198#35362198 – Matthew Taylor Feb 11 '18 at 13:54
1

VHDL is perfectly adequate for writing a parser, especially if you can massage the source format in whatever generates it, into something with a reasonably simple grammar. – Feb 11 '18 at 18:11
@BrianDrummond it is indeed possible, but in my experience parsing data in VHDL slows down elaboration. It's much faster to preformat/generate the data (using python or so) so the VHDL code only has to read it. You could script this. – JHBonarius Feb 12 '18 at 09:16
@JHBonarius Agreed on massaging the data elsewhere first; that's what I was hintisg at with "simple grammar". As for slowing down elaboration ... that's very tool dependent, but if you're stuck with the wrong tool ... you're not wrong. Xilinx XST (old parser) had some stupid square law algorithm that blew up a sub-second elaboration in anything else to over an hour. Asserting every LUT entry, you could see it slowing down... – Feb 12 '18 at 10:36

How can I initialize an array of length 1 in VHDL

1 Answers1

With explicit index

With others

With `others`