I'm trying to dump internal signals from a simulation executed either by modelsim or ghdl. Everything works fine using:
For modelsim, add vhdl sources, and compile all then:
vsim -novopt work.uut_testbench
vcd file ../uut.vcd;
vcd limit 50000000;
vcd add -r /uut_testbench/uut_core/*;
run 6000
quit -sim
For GHDL
ghdl -i --ieee=synopsys --warn-no-vital-generic --workdir=work --work=work ./uut*.vhd
ghdl -m --ieee=synopsys --warn-no-vital-generic --workdir=work --work=work uut_testbench
./uut_testbench --stop-time=6000ns --vcd=../uut.vcd
I can see simulation signals, but not all. Signals defined as
Type InternalState is (Idle,Valid,Stalled);
Signal sState,sPrevState :InternalState;
are omitted from the vcd. This behavior is common for modelsim and ghdl.
I can see the following line at the ghdl-generated vcd
$comment sstate is not handled $end
Modelsim just omits those signals quietly
Is there a workaround? Alternative?