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Is there any AXI4Lite slave IP (Verilog, VHDL) available under GNU GPL? I want to test a virtual AXI4 master in a uP system and hence this requirement.

Just an AXI4 slave or AXI3 slave will also do (I can strip down the signals to make it AXI4Lite compatible).

Any links, source code will be helpful.

artless noise
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dpaul
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  • Is there a strong requirement for GNU GPL? Major FPGA houses (e.g. Xilinx) provide a libraries of AXI compatible IP (many of which are slave devices), some of which include source delivery. But this IP is not licensed as GNU GPL. – Josh Feb 19 '15 at 13:51
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    Look at http://opencores.org/project,axi4_tlm_bfm –  Feb 19 '15 at 15:59
  • Thanks Josh! No there isn't a strong requirement for GNU GPL. Can you please elaborate a bit, how to obtain such a slave IP from Xilinx. I tried to generate one using Coregen using the normal ISE license, but didn't succeed since a separate license feature XILINX_AXI_BFM is required. – dpaul Feb 19 '15 at 16:06
  • You will probably need to contact a Xilinx sales rep as most IP cores require you to purchase separate licenses. I'm not sure if Xilinx still does this (thought they use to), but I know Altera lets you at least generate some cores and compile them into your design on a "trial" bases. They enforce this by forcing you to load the FPGA build over JTAG only. You can ask if Xilinx has something similar if you want to be sure the core suites your needs before committing to purchase. – pwolfsberger Feb 20 '15 at 15:50
  • THanks Brian & pwolfsberger! – dpaul Mar 02 '15 at 09:14

2 Answers2

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You can use AXI slave template implemented in the following repository (VHDL, BSD license): https://github.com/sergeykhbr/riscv_vhdl

File types_nasti.vhd implements general methods to work with the AXI bus. NASTI is the other name of the AXI interface invented by this team http://riscv.org to avoid trademark usage problems.

The project structure is very similiar to Gailser's LEON3 implementation but it implements 64-bits Rocket-Chip CPU (RISC-V ISA) and several AXI4 modules: UART, GPIO, IRQ controller etc.

sergey
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A clear idea about AXI protocol can be obtained at AMBA AXI and ACE Protocol Specification AXI3, AXI4, and ....

Other opencore small purpose IP is available at opencore website.

Many YouTube videos are also helpful for beginners. video site.

A detailed understanding about AXI IP is a must thing for designing it.

rahulcodesinverilog
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