I'm having difficulty understanding the Operating State of the APB Protocol. In the diagram, the state ACCESS goes back to SETUP state when PREADY = 1 and there is a transfer. Also, it describes that
The bus only remains in the SETUP state for one clock cycle and always moves to the ACCESS state on the next rising edge of the clock.
How do I evaluate the state in clocks 5-9 in the waveform below?
Clk State
1 IDLE
2 SETUP
3 ACCESS
4 ACCESS
5 SETUP ? (following PREADY = 1 and transfer)
6 ACCESS ? (SETUP always goes to ACCESS after 1 cycle)
7 IDLE ? (PREADY = 1 and no transfer)
8 ACCESS ? (since PSEL = PENABLE = 1 and PREADY = 0)
9 ACCESS ?
1 2 3 4 5 6 7 8 9
_ _ _ _ _ _ _ _ _
clk _| |_| |_| |_| |_| |_| |_| |_| |_| |_
_______________ ___________
psel _____| |___|
___________ _______
penable _________| |_______|
___________ ___
pready _________________| |___|