2

I am just looking for advice. I currently have a custom IP integrated in VHDL which has a AXI4 slave input and an AXI4 master output, and currently the signals are directly tied together.

I would like to add a customizable latency to the AXI signals, so that way they can be delayed for a particular amount of time through the IP, rather than being connected to each other.

My question is; can I delay read and write transactions through the IP merely through the use of the AxVALID and AxREADY (and maybe the RVALID/RREADY and WVALID/WREADY) signals?

If for instance I wanted a 20 clock cycle delay, I could wait for an external master to assert VALID, and wait 20 clocks before having the IP slave assert READY? Is this correct logic?

Thanks in advance for any any advice.

MateoConLechuga
  • 561
  • 4
  • 23
  • 2
    By delaying the AxREADY signals you impact the throughput, that is, the maximum number of transactions per second. If you really want to control the latency (delay between requests and responses), you should, instead, add a FIFO on the responses path (RVALID-RDATA-RRESP and BVALID-BRESP). – Renaud Pacalet Jul 07 '17 at 06:08
  • @RenaudPacalet is there a big difference between the two? It seems to me that using a FIFO would have the same impact; unless I'm mistaken? – MateoConLechuga Jul 07 '17 at 06:13
  • 2
    Yes, there is a big difference. If you delay the request acknowledges (AxREADY), you prevent the master from issuing more requests. If you acknowledge the requests but delay the responses (RVALID and BVALID), instead, you increase the latency between requests and responses, but you do not prevent the master from issuing more requests, if it can. If the master supports it, you can even keep the original throughput while increasing the latency. – Renaud Pacalet Jul 07 '17 at 06:24

1 Answers1

3

Yes, that can be done. Depending on your infrastructure it can cause bus congestion. Alternatively, you should also insert a FIFO to buffer these delayed bus transactions.

Paebbels
  • 15,573
  • 13
  • 70
  • 139