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I have been looking for some documentation on the case when ARVALID and AWVALID both go high in the same clock and contain the same address. Should the write be handled first, or should the read? Any help is much appreciated.

MateoConLechuga
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  • Please remove the vhdl and hdl tags. Your question has nothing to do with them. You can probably also remove vlsi. – Renaud Pacalet Jul 19 '17 at 05:47
  • What are you interfacing via AXI4? The purpose may define which of read or write should occur first. –  Jul 19 '17 at 09:39

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AXI4 does not specify this. It is up to you to decide and then to implement this in your interconnect or in your slave.

Renaud Pacalet
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  • AMBA AXI and ACE Protocol Specification, AXI3, AXI4, and AXI4-Lite ACE and ACE-Lite Issue D 2011 - A3.3 Relationships between the channels, The AXI protocol requires the following relationships to be maintained: • a write response must always follow the last write transfer in the write transaction of which it is a part • read data must always follow the address to which the data relates • channel handshakes must conform to the dependencies defined in Dependencies between channel handshake signals *(A3.3.1)*. Otherwise, the protocol does not define any relationship between the channels. –  Jul 19 '17 at 09:31
  • @user1155120 My intuition is that the question was more about simultaneous read and write at the **same** address, not really the transaction dependencies as depicted in section A3.3. I may be wrong. – Renaud Pacalet Jul 19 '17 at 09:46
  • The quote was to encourage authoritative answers. The operative portion *Otherwise, the protocol does not define any relationship between the channels.* That can extend to address spaces. By definition the question is unclear, notwithstanding intuition. –  Jul 19 '17 at 10:13