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Questions tagged [pci-e]

PCI-Express (PCIe) is a peer 2 peer interconnect which is based on PCI and PCI-X. Newest generation is gen 5.0. PCIe is maintained and developed by PCI-SIG.

Versions

  • PCIe Gen1 -- Released in 2003, PCIe Gen 1 supports bandwidth of 2.5 GT/s per lane per direction.
  • PCIe Gen2 -- Released in January 2007. PCIe Gen 2 supports bandwidth of 5 GT/s per lane per direction.
  • PCIe Gen3 -- Released in November 2010. PCIe Gen 3 supports bandwidth of 8 GT/s per lane per direction.
  • PCIe Gen4 -- Released in November 2011. PCIe Gen 4 supports bandwidth of 16 GT/s per lane per direction.
  • PCIe Gen5 -- Released in June 2017. PCIe Gen 5 supports bandwidth of 32 GT/s per lane per direction.

References

PCIe (Wikipedia)

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What is the Base Address Register (BAR) in PCIe?

After going through some basics documents what I understood is, Base Address Register is Address space which can be accessed by PCIe IP. PCIe IP can either transmit data in Base Address Register or it can write received data on to it. Am I right? Or…
tollin jose
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How to do a TRUE rescan of PCIe bus

I have an FPGA (Like most of the people asking this question) that gets configured after my Linux kernel does the initial PCIe bus scan and enumeration. As you can guess, the FPGA implements a PCIe endpoint. I would Like to have the PCIe core…
whh4000
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How can the linux kernel be forced to enumerate the PCI-e bus?

Linux kernel 2.6 I've got an fpga that is loaded over GPIO connected to a development board running linux. The fpga will transmit and receive data over the pci-express bus. However, this is enumerated at boot and as such, no link is discovered…
reign_man
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How does DMA work with PCI Express devices?

Let's suppose a CPU wants to make a DMA read transfer from a PCI Express device. Communication to PCI Express devices is provided by transaction layer packets (TLP). Theoretically, the maximum payload size is 1024 doubleword for TLP. So how does a…
spartacus
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PCI Express BAR memory mapping basic understanding

I am trying to understand how PCI Express works so i can write a windows driver that can read and write to a custom PCI Express device with no on-board memory. I understand that the Base Address Registers (BAR) in the PCIE configuration space hold…
user3156702
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Understanding segment group, bus, device and function numbers from SMBIOS

Objective I'm trying to programmatically find out on which physical slot a particular PCIe device is connected. The premise is that I have the PCI-ID of a card that is surely occupying a slot, and the solution would be finding out which one. Note…
C2H5OH
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How is a PCI / PCIe BAR size determined?

I know that the base address register (BAR) in PCI configuration space defines the start location of a PCI address, but how does the size of this region get established? Surely this is a property of the hardware since only it knows how far into its…
JeffV
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Interrupt routing for PCIe slot directly connected to the CPUs

If we look at a Haswell architectural diagram today we can see that there are PCIe lanes directly connected to the CPU (for graphics) as well as some of them routed to the the platform controller hub (southbridge replacement): If we look Intel 8…
zgerd
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Difference between memory bus and address bus

Can someone very briefly point out the differences between the memory bus and address bus in computer architectures ? Also when you say memory bus does it imply that you are referring to the databus ?
Navneeth Baliga
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difference between pci_alloc_consistent and dma_alloc_coherent

I am working on pcie based network driver. Different examples use one of pci_alloc_consistent or dma_alloc_coherent to get memory for transmission and reception descriptors. Which one is better if any and what is the difference between the two?
bdubey
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Enabling write-combining IO access in userspace

I have a PCIe device with a userspace driver. I'm writing commands to the device through a BAR, the commands are latency sensitive and amount of data is small (~64-bytes) so I don't want to use DMA. If I remap the physical address of the BAR in the…
Chiggs
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How is PCI segment(domain) related to multiple Host Bridges(or Root Bridges)?

I'm trying to understand how PCI segment(domain) is related to multiple Host Bridges? Some people say multiple PCI domains corresponds to multiple Host Bridges, but some say it means multiple Root Bridges under a single Host Bridge. I'm confused…
Zihan
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What is DMA mapping and DMA engine in context of linux kernel?

What is DMA mapping and DMA engine in context of linux kernel? When DMA mapping API and DMA engine API can be used in Linux Device Driver? Any real Linux Device Driver example as a reference would be great.
Jagdish
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Large PCIe DMA Linux x86-64

I am working with a high speed serial card for high rate data transfers from an external source to a Linux box with a PCIe card. The PCIe card came with some 3rd party drivers that use dma_alloc_coherent to allocate the dma buffers to receive the…
LINEMAN78
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Linux PCI Driver Setup and Teardown

After looking at the kernel docs here: https://www.kernel.org/doc/Documentation/PCI/pci.txt I am lost as to the ordering of function calls to set up and tear down a PCI driver. I have two questions: For setup, does pci_enable_device() always come…
It'sPete
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