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I am wondering about Data Bus Exceptions for the MicroBlaze. In the MicroBlaze product manual it states that the exception can only occur on M_AXI_DC when the cache is turned off? This doesn't make sense to me; does it mean that if an error response is given on the M_AXI_DC line, no exception will be triggered if caching is enabled? I currently have C_DCACHE_ALWAYS_USED set to 1 so that is not an issue.

Thanks.

Excerpt from MicroBlaze product guide:

The data cache AXI4 interface (M_AXI_DC) exception is caused by:

    - An error response on M_AXI_DC_RRESP or M_AXI_DC_BRESP,
    - OKAY response on M_AXI_DC_RRESP in case of an exclusive access using LWX.

The exception can only occur when C_DCACHE_ALWAYS_USED is set to 1 and the
cache is turned off
MateoConLechuga
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1 Answers1

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Based on my hardware/software tests and using an AXI BRAM Controller to generate ECC fault injections, the MicroBlaze will not issue an data or instruction cache exception if caching is enabled, even if caching is disabled right before writing; and reenabled before reading to trigger the exception. This is also the case if the cache is flushed and invalidated, and then read immediately back.

This basically means that ECC is worthless in MicroBlaze designs that have caching enabled; as they do not trigger any hardware exceptions.

Even though the response by the AXI BRAM Controller is a SLVERR, the MicroBlaze will accept the data as is; as if nothing bad could possibly happen.

Who designed this. Seriously.

I guess the only surefire method is to use interrupts to detect ECC errors; which have a lower precedence than hardware exceptions.

MateoConLechuga
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