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Questions tagged [riscv]

For questions related to RISC-V assembler, compiler specifics and HDL (hardware description language) implementation and use. Note: Questions on hardware implementation will be more appropriate for the electronics engineering site: https://electronics.stackexchange.com

Summary

RISC-V (pronounced "risk-five") is an instruction set architecture (ISA) that was originally designed to support computer architecture research and education and is now a standard open architecture for industry implementations under the governance of the RISC-V Foundation. RISC-V was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley.

Features

  • A completely open ISA that is freely available to academia and industry.

  • A real ISA suitable for direct native hardware implementation, not just simulation or binary translation.

  • An ISA that avoids "over-architecting" for a particular microarchitecture style (e.g., microcoded, in-order, decoupled, out-of-order) or implementation technology (e.g., full-custom, ASIC, and FPGA), but which allows efficient implementation in any of these.

  • An ISA separated into a small base integer ISA, usable by itself as a base for customized accelerators or for educational purposes, and optional standard extensions, to support general-purpose software development.

  • Support for the revised 2008 IEEE-754 floating-point standard.

  • An ISA supporting extensive user-level ISA extensions and specialized variants.

  • 32-bit, 64-bit, and 128-bit address space variants for applications, operating system kernels, and hardware implementations.

  • An ISA with support for highly-parallel multicore or manycore implementations, including heterogeneous multiprocessors.

  • Optional variable-length instructions to both expand available instruction encoding space and to support an optional dense instruction encoding for improved performance, static code size, and energy efficiency.

  • A fully virtualizable ISA to ease hypervisor development.

  • An ISA that simplifies experiments with new supervisor-level and hypervisor-level ISA designs.

References

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RISC-V spec references the word 'hart' - what does 'hart' mean?

I found references to hart on page 35 of the RISC-V 2.1 spec. However, I could not find a definition for hart in this document. Does hart refer to a hardware-thread or something more sinister?
daveW
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RISC-V: Immediate Encoding Variants

In the RISC-V Instruction Set Manual, User-Level ISA, I couldn't understand section 2.3 Immediate Encoding Variants page 11. There is four types of instruction formats R, I, S, and U, then there is a variants of S and U types which are SB and UJ…
Ammar Kurd
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RISC-V difference between jal and jalr

I came across the instruction named jal and jalr while studying RISC-V assembly language. I quite having hard times to understand the differences between jal and jalr. jal x1, X It seems that above code is meaning that jump to X, and save the…
jwkoo
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RISC-V build 32-bit constants with LUI and ADDI

LUI (load upper immediate) is used to build 32-bit constants and uses the U-type format. LUI places the U-immediate value in the top 20 bits of the destination register rd, filling in the lowest 12 bits with zeros. I found this in manual, but if I…
Li Hanyuan
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What is meant by the FENCE instruction in the RISC-V instruction set?

While going through the RISC-V ISA, I have seen an instruction in the memory model section (FENCE instruction). What does it mean exactly?
Aneesh Raveendran
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How can I compile C code to get a bare-metal skeleton of a minimal RISC-V assembly program?

I have the following simple C code: void main(){ int A = 333; int B=244; int sum; sum = A + B; } When I compile this with $riscv64-unknown-elf-gcc code.c -o code.o If I want to see the assembly code I…
Adrian
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Why are RISC-V S-B and U-J instruction types encoded in this way?

I am reading a book "Computer Organization and Design RISC-V Edition", and I came across the encoding for S-B and U-J instruction types. Those types I have mentioned above has strange encoded immediate field. S-B types separate the immediate field…
jwkoo
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ABI Register Names for RISC-V Calling Convention

I'm confused about the RISC-V ABI Register Names. For example, Table 18.2 in the "RISC-V Instruction Set Manual, Volume I: User-Level ISA, Version 2.0" at page 85 specifies that the stack pointer sp is register x14. However, the instruction addi…
CliffordVienna
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x86 Program Counter abstracted from microarchitecture?

I'm reading the book The RISC-V Reader: An Open Architecture Atlas. The authors, to explain the isolation of an ISA (Instruction Set Architecture) from a particular implementation (i.e., microarchitecture) wrote: The temptation for an architect is…
JFMR
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What is the definition of JAL in RISC-V and how does one use it?

I don't get how JAL works in RISC-V as I've been seeing multiple conflicting definitions. For example, if I refer to this website: https://rv8.io/isa.html It says that: JAL rd,offset has the 3rd argument as the offset, but there are some cases that…
winnie99
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RISC-V ecall syscall calling convention on pk/Linux

What is the calling convention for a syscall in a program that runs under the RISC-V pseudo-kernel (pk) or Linux? Looking at the code generated by the riscv-gnu-toolchain the rules seem to be: syscall number is passed in a7 syscall arguments are…
maxschlepzig
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RISC-V NOP instruction

I am working on RISC-V 32I instructions recently. I got a question about NOP instruction, which the specification says it is equal to ADDI x0, x0, 0. However, x0 is not a general register which can be modified by the programmer. Thus, why x0 serves…
Betty
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RISC-V assembly simulator

I'm trying to learn the RISC-V ISA. Is there a way to simulate RISC-V assembly code just like in MARS for the MIPS ISA?
hypergamer003
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Learning Chisel -- advanced examples to understand Rocket Chip code

The Berkeley implementation of RISC-V is called Rocket Chip and it is written in a hardware language called Chisel. Chisel is object oriented, and it has been difficult for the people on our team to learn to the point of being effective at modifying…
seanhalle
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What is RISC-V and how does it compare to previous RISC architectures?

What is RISC-V? Why was it created? What improvements does it have over previous RISC architectures? (This is meant to be a wiki for RISC-V on StackOverflow.)
user541686
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