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If I perform a store into the L1 Dcache does the Rocket Chip core produce a resp valid signal or is that only for a load signal? Cos for a load signal you are requesting something and you get something in response whereas for the store you just need to check if the memory interface is ready and send out the signal. (I am talking about the io.mem.resp field)

Jack Koenig
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CV_Ruddha
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1 Answers1

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I figured out the answer. In short while performing a store operation it is just a ready-valid interface.

CV_Ruddha
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  • Hi @CV_Ruddha, I was trying to use io.mem rocc interface for multiple store operation. I observed store operation didn't get any acknowledge over io.mem.resp interface which is fine in case processor-dcache transaction; But in case of co-processor's rocc interface there's simplehellacache block and arbiter in between co-processor and L1 Dcache. and I observed SimpleHellacache Block stalls io.mem.req interface if two consecutive store operation initiated. Can I get some tips for rocc's io.mem.req and io.mem.resp interfaces (especially for store)? It'll really helpful for me thanks. – Sanket Khandare Feb 27 '20 at 04:39
  • Where did you see that there is a SimpleHellaCache block and an arbiter between co processor and L1 D cache? If you have a diagram attach it. I wanna understand what you mean. Also to understand the connections go through the AccumulatorExample in LazyRoCC.scala file. It shows how to read and write from D cache. – CV_Ruddha Feb 27 '20 at 19:01
  • Unfortunaely I don't have diagrams. I went through generated verilog source code for AccumlatorExample.There is SimpleHellaCacheIf block in between L1 Dcache and co-processor. I modified LazyRocc.scala for initiating multiple load and store operations from co-processor.It works fine with multiple load but I'm struggling with multiple store. You can see scala script for simplehellacacheif over here: https://github.com/chipsalliance/rocket-chip/blob/319b6c44450ccde38f33cd8a38dd80071a0b6528/src/main/scala/rocket/SimpleHellaCacheIF.scala#L65. – Sanket Khandare Feb 28 '20 at 04:40
  • Ah, I guess you are getting a simplehellacache exception error, I don't think you need to alter the SimpleHellaCacheIF file. You get an error when the ready valid signals aren't being asserted properly. To perform multiple stores you need to make sure that the ready valid signals are being produced properly. Maybe a state diagram might help where you stay in the store state until you have finished all your stores. – CV_Ruddha Feb 28 '20 at 08:14
  • I'm not getting an error or assertions.I've written code using state machine only. My state machine got stuck (with io.mem.req.valid high)because it's waiting for io.mem.req.ready signal but it didn't raise from memory side after two store operations.At the same time i check Dcache interface it raised ready signal and waiting for valid. So i checked path in between and there i found this SimpleHellaCacheIf. Something is going on inside SimpleHellaCache and im curious about it. – Sanket Khandare Feb 28 '20 at 10:07
  • Actually My code is combination of load-store operation and it is implemented using state machine.whole code won't fit here.I'm putting some blocks.. – Sanket Khandare Mar 02 '20 at 04:47
  • `when(state === s_write)` `{` `io.mem.req.valid := Bool(true)` `io.mem.req.bits.tag := counter` `io.mem.req.bits.size := log2Ceil(4).U` `io.mem.req.bits.signed := Bool(true)` `io.mem.req.bits.phys := Bool(false)` `io.mem.req.bits.cmd := M_XWR` `io.mem.req.bits.data := memory(counter%4.U) + memory((counter%4.U)+4.U)` `io.mem.req.bits.addr := (destination)+((counter%4.U) * 4.U)` `}` – Sanket Khandare Mar 02 '20 at 04:53
  • these all assignment in write state. And all values assigned to combinational val(no reg). – Sanket Khandare Mar 02 '20 at 04:57