To test my Chisel designs I'm using Icarus with cocotb. But Icarus doesn't generate VCD traces if it's not asked explicitly in verilog module code like this :
`ifdef COCOTB_SIM
initial begin
$dumpfile ("my_module_name.vcd");
$dumpvars (0, my_module_name);
#1;
end
`endif
To add this each time I generate my chisel module, I wrote a little python script named cocotbify.py that "inject" this code under the module generated.
Similarly, to add some systemVerilog assert()/assume() for Formal checking with yosys-smtbmc I have to "inject" code under each verilog modules generated. I also hacked a little python script named smtbmcify.py to inject my assert/assume codes.
I realize that is a hack, but I can't found a good way to do it directly under the Chisel module. I know that there are BlackBox, but I don't wan't to instanciate a submodule, and the function setInline create a second verilog file (I want to write in module directly).
I saw a type named ChiselAnnotation in Chisel scala code, But I'm not sure that is the things to use and I don't now how.
