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Questions tagged [yosys]

Yosys is an open-source framework for (Verilog) HDL synthesis and formal verification. It is highly customizable using scripts and a C++ extensions API.

Yosys is an open-source framework for (Verilog) HDL synthesis and formal verification. It is highly customizable using scripts and a C++ extensions API.

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How to inject Verilog code in Chisel generated Module?

To test my Chisel designs I'm using Icarus with cocotb. But Icarus doesn't generate VCD traces if it's not asked explicitly in verilog module code like this : `ifdef COCOTB_SIM initial begin $dumpfile ("my_module_name.vcd"); $dumpvars (0,…
FabienM
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iCEstick + yosys - using the Global Set/Reset (GSR)

This is probably more of an iCEstick question than a yosys one, but asking here since I'm using the Icestorm tool chain. I want to specify startup behavior of my design, which various places on the internet seem to agree is related to the typically…
Myles Hathcock
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Is it possible to create a simulation waveform from yosys output

I've found simulating using iverilog to be a less than suitable method, I can simulate designs that won't synthesise and conversely designs that will not only synthesize but also work as intended on physical hardware, won't synthesise with iverilog…
Chris Camacho
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Can we have variables in a Yosys script?

I'd like to make my Yosys scripts more DRY by factoring out common parameters, such as in the following example: read_liberty -lib /long/path/to/lib/file ... dfflibmap -liberty /long/path/to/lib/file ... abc -liberty /long/path/to/lib/file I…
FriendFX
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How can I use iCE40 4K block RAM in 512x8 read mode with IceStorm?

I am trying to figure out how to use the block RAM on my iCE40HX-8K Breakout Board. I would like to access it in a 512x8 configuration, which as far as I can tell from the documentation is supported by project IceStorm, but I haven't been able to…
Josh Headapohl
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How do I use set LVDS mode on Lattice ICE40 pins using ICESTORM tools

I have a Lattice ICE40_8K breakout board and would like to know how to setup a pin pair as LVDS mode inputs. If setting up as normal single pins is done thus: SB_IO #(.PIN_TYPE(6'b0000_00)) _io ( .PACKAGE_PIN(pin), .INPUT_CLK(clk), …
Bernard Mentink
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iCE40 IceStorm FPGA Flow: Bi-directional IO pins

Using the iCE40 FOSS IceStorm FPGA flow: how does one write Verilog for a 3-state I/O pin (like a bidirectional data bus pin) using yosys/iceStorm?
CliffordVienna
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FSM export using Yosys

I am using Yosys to synthesize my Verilog designs. I want to export the FSM in my Verilog design using the Yosys command fsm_export, but it does not generate anything. I wonder how is this command supposed to be called. The series of commands I…
adrianX
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What is required to target a new device?

From a high-level point of view, what is required to target a new device with Yosys? I'd like to target a Xilinx XC9572XL. I have one these development boards: XC9572XL-CPLD-development-board-v1b. The architecture of this CPLD is fairly well…
Mike Wright
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What is a good "template" Yosys synthesis script?

I want to write my own Yosys synthesis script. What is a good template to start with? The manual and webpage contain various examples, but no "authoritative" hello world example.
CliffordVienna
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What are yosys formal capabilities with verific?

I'm trying to use Yosys formal verification capabilities along with Verific parser. What are the supported capabilities of yosys with verific for formal verification, compared to the "read_verilog -formal" command? For example, a quick compilation…
EEliaz
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Parameters to Script

Is there some way to pass parameters (or command line arguments) to a Yosys script? I see in this quetion (Can we have variables in a Yosys script?) you can run the Yosys script within a TCL interpreter. Is there some way to pass in an…
jgoeders
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Understanding the bitstream generated for iCE40 I/O tiles

When I synthesize an empty circuit using Yosys and arachne-pnr, I get a few irregular bits: .io_tile 6 17 IoCtrl IE_1 .io_tile 6 0 IoCtrl REN_0 IoCtrl REN_1 These are also part of every other file I could generate so far. Since an unused I/O tile…
rlutz
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Computed verilog parameter in Yosys

I am learning Verilog at the moment by using Yosys to synthesize code to an iCE40 development board. I am stuck at using parameters in verilog. I have the following code: module tst; parameter clkspd=12000000; parameter baudrate=115200; …
T. van Staden
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Netlist validation using Yosys

I'd like to ask if I can validate my design in yosys. I re-synthesized my netlist, used yosys to get the execution (topological order). Now I want to check the validation of this design by inserting some inputs to the netlist and check the output. …
Never too late
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