Is it possible to create a simulation waveform from yosys output

Question

I've found simulating using iverilog to be a less than suitable method, I can simulate designs that won't synthesise and conversely designs that will not only synthesize but also work as intended on physical hardware, won't synthesise with iverilog for simulation.

What I'm ideally looking to do take the output of yosys (a blif file) and create a simulation waveform (vcd) that I can have better confidence in.

Maybe offtopic, but if vhdl is an option, I never had an issue with ghdl waveforms. — xvan, Mar 10 '16 at 21:49
yosys is part of the open source Verilog tool chain for the iCEstick & board — Chris Camacho, Mar 11 '16 at 00:39
@Paebbels Yosys is an Open Source Verilog Synthesis framework and more (e.g. various forms of formal verification are available in Yosys in addition to ASIC and FPGA synthesis flows). http://www.clifford.at/yosys/ — CliffordVienna, Mar 11 '16 at 11:39

score 12 · Accepted Answer · answered Mar 11 '16 at 11:36

So you want to run post-synthesis simulation of iCE40 BLIF netlists.

Consider the following simple example design (test.v):

module test(input clk, resetn, output reg [3:0] y);
  always @(posedge clk)
    y <= resetn ? y + 1 : 0;
endmodule

And its testbench (test_tb.v):

module testbench;
  reg clk = 1, resetn = 0;
  wire [3:0] y;

  always #5 clk = ~clk;

  initial begin
    repeat (10) @(posedge clk);
    resetn <= 1;
    repeat (20) @(posedge clk);
    $finish;
  end

  always @(posedge clk) begin
    $display("%b", y);
  end

  test uut (
    .clk(clk),
    .resetn(resetn),
`ifdef POST_SYNTHESIS
    . \y[0] (y[0]),
    . \y[1] (y[1]),
    . \y[2] (y[2]),
    . \y[3] (y[3])
`else
    .y(y)
`endif
  );
endmodule

Running pre-synthesis simulation is of course simple:

$ iverilog -o test_pre test.v test_tb.v
$ ./test_pre

For post-synthesis simulation we must first run synthesis:

$ yosys -p 'synth_ice40 -top test -blif test.blif' test.v

Then we must convert the BLIF netlist to a verilog netlist so it can be read by Icarus Verilog:

$ yosys -o test_syn.v test.blif

Now we can build the simulation binary from the test bench, the synthesized design, and the iCE40 simulation models, and run it:

$ iverilog -o test_post -D POST_SYNTHESIS test_tb.v test_syn.v \
                        `yosys-config --datdir/ice40/cells_sim.v`
$ ./test_post

[..] won't synthesize with iverilog for simulation.

This is most likely because Yosys is not as strict as iverilog when it comes to enforcing the Verilog standard. For example, in many cases Yosys will except Verilog files with the reg keyword missing from wires that would require the reg keyword according to the Verilog standard. For example, yosys will accept the following input, even though it is not valid Verilog code:

module test(input a, output y); 
  always @* y = !a;
endmodule

For Icarus Verilog you have to add the missing reg:

module test(input a, output reg y); 
  always @* y = !a;
endmodule

thanks for the iverilog post synthesis tip (not to mention the great tools!) to be honest I have just as much trouble with valid iverilog code not synthesising as i have the other way round! (most of this is because I'm doing stuff through ignorance with verilog that would curl your toes!!!) BTW is ice40/cells_sim.v okay for the 8k board? — Chris Camacho, Mar 11 '16 at 15:29
@ChrisCamacho Open a ticket on github or a question here on stackoverflow if you have verilog code that you think should be working but is rejected by yosys. And yes, `ice40/cells_sim.v` is ok for iCE40 1K, 4K and 8K devices. — CliffordVienna, Mar 11 '16 at 15:38

Is it possible to create a simulation waveform from yosys output

1 Answers1