Highest Voted 'ice40' Questions

6

votes

1 answer

How do I use set LVDS mode on Lattice ICE40 pins using ICESTORM tools

I have a Lattice ICE40_8K breakout board and would like to know how to setup a pin pair as LVDS mode inputs. If setting up as normal single pins is done thus: SB_IO #(.PIN_TYPE(6'b0000_00)) _io ( .PACKAGE_PIN(pin), .INPUT_CLK(clk), …

verilog yosys ice40

asked Oct 17 '16 at 21:52

Bernard Mentink

61
3

4

votes

2 answers

Understanding the bitstream generated for iCE40 I/O tiles

When I synthesize an empty circuit using Yosys and arachne-pnr, I get a few irregular bits: .io_tile 6 17 IoCtrl IE_1 .io_tile 6 0 IoCtrl REN_0 IoCtrl REN_1 These are also part of every other file I could generate so far. Since an unused I/O tile…

yosys ice40

asked Feb 23 '17 at 18:55

rlutz

77
4

3

votes

2 answers

Using the SB_RGBA_DRV primitive in VHDL

I'm having trouble using the SB_RGBA_DRV primitive provided for the Lattice ICE40UP fpga. The Technology Library provides a verilog example which I got to work but when i try using it in VHDL the P&R fails, outputting the following message: Error:…

vhdl ice40

asked May 10 '18 at 15:58

N.Atema

63
4

2

votes

1 answer

Yosys: Multiple edge sensitivities for asynchronous reset

I am teaching myself verilog, bare with me. :) I have a clock line called enable coming from a clock divider I created. I also have a rst button on my devboard. I would like to modify the following code to react to rst button presses by turning off…

verilog signal-processing fpga yosys ice40

asked Jun 03 '22 at 00:50

Neekon Saadat

417
6
18

2

votes

1 answer

Understanding the SB_IO primitive in Lattice ICE40

I am playing with cliffordwolf/picorv32 and am having some problem understanding the following snippet in picosoc (link to source): SB_IO #( .PIN_TYPE(6'b 1010_01), .PULLUP(1'b 0) ) flash_io_buf [3:0] ( .PACKAGE_PIN({flash_io3,…

verilog fpga lattice yosys ice40

asked Mar 31 '20 at 18:59

nalzok

14,965
21
72
139

2

votes

1 answer

Cannot create a clock signal on a Lattice ICE40 FPGA

I am trying to create a 1 Hz clock signal on a Lattice ICE40 FPGA. I am writing my code in Verilog and using the Lattice Radiant software. This 1 Hz clock signal is going to be used to create a square wave. However, I don't get any output, either…

verilog fpga clock lattice ice40

asked Jan 22 '19 at 16:12

PetSven

366
3
13

2

votes

1 answer

Difference in initializing a state machine between a simulator and synthesizer

My question is regarding the first state used in a synthesized state machine. I'm working with a Lattice iCE40 FPGA, the EDA Playground for simulation and Lattice's Diamond Programmer for synthesizing. In the following example I am generating a…

vhdl simulation fpga synthesis ice40

asked May 21 '18 at 14:13

Ron

41
4

2

votes

0 answers

Can LUT cascade be used simultaneously with the carry-chain in the iCE40 FPGAs by any tools?

I try to construct the following: CO | /carry\ ____ s2 ---(((---|I0 |------------ O +------+((---|I1 | …

fpga yosys ice40

asked Mar 09 '18 at 18:34

Baard

809
10
26

2

votes

1 answer

(icestorm) do pins not specified in the pcf stay high impedance

as the title, additionally how do you specify another voltage level for single ended in/output for example LVCMOS18 - I'm guessing alas its not as easy as just an extra verb in a pcf entry...

yosys ice40

asked Aug 25 '17 at 14:45

Chris Camacho

1,164
1
9
31

2

votes

1 answer

Correspondence between iCE40 I/O blocks and package pins

Is the correspondence between the I/O blocks of an iCE40 FPGA and the pins of the package they drive documented somewhere? The I/O tile documentation of Project IceStorm gives a list of I/O blocks, and for each block where its IE and REN bits are…

yosys ice40

asked Feb 23 '17 at 16:59

rlutz

77
4

1

vote

1 answer

Understanding logic tile LC_5 bits

i m new to yosys and arachne-pnr. Here is the snippet from .asc and .icebox_explain. I could not understand how the bits of LC_5 are derived from .logic_tile 1 11. example.v module top (input a, b, output y); assign y = a &…

yosys ice40

asked Jul 13 '20 at 00:01

Sajjad

111
1
13

1

vote

1 answer

Arachne-pnr internal clk reference pin

I wanted to know the internal clk reference pin number to be added for arachne-pnr pcf file. I am synthesizing for Alchitry Cu Board having the iCE40 HX8k chip (supported by yosis and arachne). I couldnt understand the correlation between pin number…

fpga ice40

asked Feb 29 '20 at 14:14

BHARAT R

13
3

1

vote

2 answers

How to program Lattice iCE40 ultra with a microcontroller

I am trying to program a iCE40 ultra FPGA with a stm32F4 microcontroller and I am trying to figure out how to load the configuration file onto the micro so that it can be sent to the FPGA by SPI to program it. The application note says that this can…

c fpga stm32f4 ice40

asked Sep 10 '19 at 19:53

jsmith95

13
3

1

vote

1 answer

Trouble Instantiating PLL of Lattice iCE40

I have Lattice iCE40 HX8K FPGA in 256 BGA package. I want to use one of the available PLL modules to transform external clock frequency of 37MHz to internal clock for use inside of the FPGA of 74MHz. I used the "Configure PLL Module" in IceCube2…

vhdl fpga ice40

asked Jun 01 '19 at 07:15

Vasil

21
5

1

vote

3 answers

How to reuse BRAM once it's not needed by module?

I'm working on a (seemingly) simple project as a learning exercise: connecting an SSD1331-based 96x64 PMOD display via iCEstick (Lattice iCE40HX-1k FPGA) to PC so I can send some RGB565-encoded image through USB to be shown on said display. Thing…

fpga yosys ice40

asked Dec 24 '18 at 08:08

Viking

328
4
9

Questions tagged [ice40]