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I wanted to know the internal clk reference pin number to be added for arachne-pnr pcf file. I am synthesizing for Alchitry Cu Board having the iCE40 HX8k chip (supported by yosis and arachne). I couldnt understand the correlation between pin number in pcf file to pin of the chip...

If someone could give me an example pcf file for say a DFF (something using clock), I will figure out the remaining. I have searched for this in google but was unsuccessful.

I saw some reference on .gate... command but didn't understand whether it should be added to pcf file or some other file and compiled for clk output. If so, please give me that command example

Sorry, for the long question. Any help will be much appreciated.

Thanks, Bharat

BHARAT R
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  • I also have had this problem with Lattice systems, but I've found useful things in github repositories like https://github.com/damdoy/ice40_ultraplus_examples it might be worth looking through some of these repositories and seeing if there are any examples already for the lattice system you're using. Voting up, because this is an incredibly useful question and causes a lot of consternation for people who are new to Lattice systems. – Owl Feb 29 '20 at 15:09
  • Yeah, such little support. Am trying to figure it out myself. Will update if something clicks – BHARAT R Feb 29 '20 at 15:34
  • What is the relation between J5,A8,J3 (so called clock). If I try to compile this using arachne-pnr it shows an error. It needs numbers 78,82 etc. From the schematic one can determine the pin name. But how will you get this number – BHARAT R Feb 29 '20 at 15:44

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pin numbers in the PCF are the same as package pin numbers. ".gate" is in the BLIF file generated by the synthesis tool and not something you put in the PCF.

Also do note that arachne-pnr is now deprecated and largely unsupported, you should be using its successor nextpnr for open source place and route. Its handling of PCF issues should be better too.

gatecat
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