Cannot create a clock signal on a Lattice ICE40 FPGA

Question

I am trying to create a 1 Hz clock signal on a Lattice ICE40 FPGA. I am writing my code in Verilog and using the Lattice Radiant software. This 1 Hz clock signal is going to be used to create a square wave.

However, I don't get any output, either from the pin the clock signal is supposed to be on or from the pin that is supposed to output a square wave. I am sure I am checking the correct pins. I am also sure the code is downloading to the board. I believe the FPGA is not actually creating the clock signal for some reason.

Here is my code:

module square (clk, x, y, z);

// Inputs and Outputs
input clk; // The clock signal
output x, y, z; // The square wave output

// Type Declaration
reg x; // x is a register

// Initialize x
initial
    begin
        x = 0;
    end

// Run each time the clock transitions from low to high
always @(posedge clk)
    begin 
        x = !x; // Flip x
    end

// Outputs used to confirm the program is running   
assign y = 0; //39A
assign z = 1; //41A

endmodule

And here is my synthesis constraint file (.ldc):

create_clock -name {clk} -period 1000000000 [get_ports clk]

The period is defined in nanoseconds, so this a 1 Hz clock.

Thank you.

Where is `clk` coming from? Really all your `square` module does (besides the static `y` and `z` assignments) is make `x` a copy of `clk`, where `clk` is expected to be a proper clock and `x` is the output of a LUT or register (if it's not synthesized away entirely). Defining a `create_clock` constraint does not magically create a clock at the specified frequency. `create_clock` is just a way to inform STA and routing processes of the characteristics of the clock. You still need to actually generate the clock somewhere. — Kevin Kruse, Jan 22 '19 at 17:43
If you want to create a clock on an FPGA, you need to derive it from a clock source. Development boards will have an oscillator, like 20MHz, on the board. You would divide that 20MHz down to the frequency you want, or use a PLL to create a new frequency from it. — Kevin Kruse, Jan 22 '19 at 17:45
Because edits to comments are time-gated: My mistake. `x` becomes half the frequency of `clk`. The rest of the issues still stand, you need to make `clk` somehow. — Kevin Kruse, Jan 22 '19 at 17:52

score 2 · Accepted Answer · answered Jan 22 '19 at 21:32

Thanks everyone. I did not realize I needed to create the clock myself. I have created a clock using a high speed oscillator function:

// Initialize the high speed oscillator
HSOSC clock (
    .CLKHFEN(1'b1), // Enable the output  
    .CLKHFPU(1'b1), // Power up the oscillator  
    .CLKHF(clk) // Oscillator output  
);

// Divide the oscillator down to 6 MHz
defparam clock.CLKHF_DIV = "0b11";

And it appears to be working.

Cannot create a clock signal on a Lattice ICE40 FPGA

1 Answers1