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as the title, additionally how do you specify another voltage level for single ended in/output for example LVCMOS18 - I'm guessing alas its not as easy as just an extra verb in a pcf entry...

Chris Camacho
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Pins not specified in the PCF are configured as pull up. (This is the same behavior with IceStorm and the Lattice iCE40 tools.)

Arachne-pnr does not provide a mechanism in PCF to specify an IO standard as this is purely informal anyways (the bitstream is the same for all IO standards, the IO voltage on an IO pin only depends on the supply voltage for that bank). The SB_IO primitive does support the IO_STANDARD parameter for better compatibility with the Lattice tools, but it is completely ignored.

I'm guessing alas its not as easy as just an extra verb in a pcf entry

If you just want to ignore it, then it is exactly that easy. If you also want to check if all IO standards on a bank are compatible than that would require a bit more work.

CliffordVienna
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  • is there anyway to make a pin (at different times) high impedance like for example in a tri state bus ? – Chris Camacho Aug 31 '17 at 13:40
  • I notice the SB_IO OUTPUT_ENABLE if set to zero set to hi-Z but its not clear how to do this in actual verilog and further how to later undo it. I have just about managed to set an input tied high but thats like a one shot instancing thing so don't understand how the SB_IO primitive and verilog interact – Chris Camacho Aug 31 '17 at 13:47