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I am playing with cliffordwolf/picorv32 and am having some problem understanding the following snippet in picosoc (link to source):

SB_IO #(
    .PIN_TYPE(6'b 1010_01),
    .PULLUP(1'b 0)
) flash_io_buf [3:0] (
    .PACKAGE_PIN({flash_io3, flash_io2, flash_io1, flash_io0}),
    .OUTPUT_ENABLE({flash_io3_oe, flash_io2_oe, flash_io1_oe, flash_io0_oe}),
    .D_OUT_0({flash_io3_do, flash_io2_do, flash_io1_do, flash_io0_do}),
    .D_IN_0({flash_io3_di, flash_io2_di, flash_io1_di, flash_io0_di})
);

I have found a graphic description for the SB_IO primitive in Lattice iCE40 technology library documentation, but I still cannot understand its purpose because it's too complex for me to interpret. There is another question about the primitive, after reading which I would assume it creates some kind of bidirectional connection, but I failed to understand how that is related to making the output pin "tristated".

I would appreciate a high-level description of the effect of the SB_IO cell under this particular configuration. Which pin is connected to which pin? Which are inputs and which are outputs? What is the purpose of instantiating this cell?

E_net4
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nalzok
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  • The only things that don't show a ready correlation between the 4 Verilog pins an the SB IO pad on P.87 of the PDF you provide the link for is what's connected to the pad pins (flash_io_buf [3:0]). .PIN_TYPE describes how the multiplexers are programmed. There is no pull-up and the latches appear unused. Is there a programming question here or are you asking a hardware question on the wrong site? –  Apr 01 '20 at 06:59
  • Hi @user1155120, I suppose asking about the effect of a cell instantiation count as a programming question? Here is the background in case you are interested: I have just learned the basics of Verilog, but have never seen FPGA "primitives" like `SB_IO`. The reason I am messing with this is that the instructor of my FPGA course encourages us to participate in an FPGA contest (which makes sense: that would be a great way to learn), and for that, I need to incorporate `picosoc` into my design. – nalzok Apr 01 '20 at 07:23
  • @user1155120 Also, the "pad pins" `flash_io_buf [3:0]` are not used hereafter, so this instantiation must have some kind of side effects? – nalzok Apr 01 '20 at 07:26
  • They're IO pins. –  Apr 01 '20 at 07:29
  • @user1155120 "IO pins" refer to the pins outside of the chip package, right? I thought `flash_io3, flash_io2, flash_io1, flash_io0` are IO pins, rather than `flash_io_buf [0:3]` o_O. – nalzok Apr 01 '20 at 07:31
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    [This question is being discussed on Meta](https://meta.stackoverflow.com/questions/396157/how-can-i-improve-my-question-about-fpga-programming). – Cody Gray - on strike Apr 02 '20 at 07:34

1 Answers1

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This instance was used because at the time Yosys didn't support tristates in Verilog well enough, it does now but in general tristate support in FPGA toolchains isn't always trusted.

It could be replaced with the following generic Verilog, repeated 4 times from 0 to 4.

assign flash_io0 = flash_io0_oe ? flash_io0_do : 1'bz;
assign flash_io0_di = flash_io0;
gatecat
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  • Thanks, that’s really helpful! I wonder what is `flash_io_buf` as mentioned above by @user1155120. Is, say, `flash_io_buf[0]` an alias of `flash_io0` after the inference/instantiation? – nalzok Apr 02 '20 at 08:55
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    `flash_io_buf[0]` is the name of the SB_IO **instance**, it has nothing to do with wires or pins – gatecat Apr 02 '20 at 10:03