What is a good "template" Yosys synthesis script?

Question

I want to write my own Yosys synthesis script. What is a good template to start with? The manual and webpage contain various examples, but no "authoritative" hello world example.

Answer 1

The synth command runs the recommended script for general-purpose synthesis tasks. See help synth for a complete list of commands called by this meta-command.

Your script should either borrow from synth or simply call synth to get the general-purpose stuff done. Many scripts call synth -run coarse for the coarse-grain part of synthesis and then continue with a custom sequence of commands for fine grains synthesis. See for example synth_xilinx.

For ASIC synthesis to a library in liberty format, use the following script as a starting point:

# read design 
read_verilog mydesign.v

# generic synthesis
synth -top mytop

# mapping to mycells.lib
dfflibmap -liberty mycells.lib
abc -liberty mycells.lib
clean

# write synthesized design
write_verilog synth.v

A less aggressive set of optimizations is often desired for scripts that do formal verification. In this cases the following sequence of commands is usually a good starting point for the "synthesis" portion of a formal verification flow:

hierarchy [-check -top <top-module>]
proc; opt; memory [-nomap]; opt -fast; check -assert

Answer 2

Don't forget to put the mycells.lib and mycells.v file in the directory where you invoke yosys. A good example is on yosys's GitHub site under the directory "examples/cmos", where they have placed examples of cmos_cell.lib and cmos_cell.v files.

read_verilog counter.v
read_verilog -lib cmos_cells.v

proc;; memory;; techmap;;

dfflibmap -liberty cmos_cells.lib
abc -liberty cmos_cells.lib;;

write_verilog synth.v

(Also, if you want a more human readable synthesis output you can modify the .lib and .v file to change NAND and NOR gates into AND and OR gates.)