I'm having trouble using the internal oscillator for the Lattice ICE5LP4K. Per the iCE40 Oscillator Usage Guide Appendix, the code in verilog should look like this:
SB_HFOSC OSCInst0 (
.CLKHF_EN(ENCLKHF),
…
I'm using active-hdl to simulate my FPGA designs and I'd like to know if it's possible to use dynamically generated strings to represent my signals in the simulator. For example, let's say I have a 4-bit std_logic_vector containing an op-code, I'd…
I'm working on a project involving Lattice XP2-30E FPGA and analog to digital converter AD9238. Propagation delay from CLK to DATA of the ad converter are specified in the datasheet as:
t_pd_ad_min=2ns
t_pd_ad_max=6ns.
Additionally, the board…
I have a (free) Lattice Diamond 3.7 installation on Windows 7 and I would like to run synthesis jobs from command line. I generated a *.prj file containing all relevant command line options, like part, toplevel and all source files.
Then I started…
I would like to use the security features in Lattice FPGA (Machxo3) and is currently stuck with Security Program Password feature.
There are two options:
security program password key
security program password key with lock
Conversation with…
I have a design where I use an IP module generated by Lattice Diamond. This uses the Macxo3l library which is shipped with diamond as a vendor library.
Using GHDL I can compile the design including this library using the instructions from…
I'm trying to use UART communication with a Lattice machox3 and a ft232R. I am trying to use the VHDL file I found on eewiki(Here). For some reason I am not being able to get tx to work when I simulate it. what am I doing wrong? Is there a simple…
I have an FPGA project with multiple VHDL files (all compile with no errors), written in Lattice's Diamond software. The problem is when I go to assign pins all I see is the inputs and outputs of one VHDL file. If I delete that file, I see another,…
I'm using Lattice Diamond 3.6
The issue I'm having is that I have my code set up to take a bunch of inputs from point A, debounce them, and then forward them to and output at B. Then, it also takes inputs from B, debounces them, and sends them to A.…
I'm new to Lattice Diamond, but I have experience with Xilinx ISE, Vivado and Quartus :).
I found - like in Xilinx ISE - that Lattice Synthesis Engine (LSE) supports generic parameters for the top-level entity. (right-click "impl1" -> Properties =>…
I'm working on learning Verilog and working with CPLDs and I'm stuck. The code I wrote toggles an LED, but I keep getting warnings during synthesis.
//toggles LED on and off after 1000000 clock cycles
module LEDON(
LED,
clk
);
output LED;
reg…
In Lattice Diamond FPGA synthesis tool, pin placement is specified through a LPF (extension .lpf) file.
However, only a single LPF file can be active at a time.
Is it possible to include another LPF file through the active LPF file, so the LPF file…
I want to program a machxO2 CPLD. There is a driver in the kernel called "machxo2-spi". This driver contains the logic on how to program the machxO2.
I successfully have it loaded and everything. I've tried to program using the driver and I can see…
I'm trying to make a Blink-LED program for a Lattice MachXO3L breakout board. I believe I have the internal-oscillator set up, I just don't know how to connect to its output and make use of it, I get errors when I try. This is on a breakout board…