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I'm new to Lattice Diamond, but I have experience with Xilinx ISE, Vivado and Quartus :).

I found - like in Xilinx ISE - that Lattice Synthesis Engine (LSE) supports generic parameters for the top-level entity. (right-click "impl1" -> Properties => HDL Parameters)

I tested it with integer parameters and it worked: A_BITS=10;D_BITS=32.
But how can I pass a string parameter?

My tests:

  1. A_BITS=10;D_BITS=32;FILENAME=ocram_sdp.mem
    This results in an unknown literal value error

    ERROR - D:/git/PoC/src/mem/ocram/ocram_tdp.vhdl(82,3-82,11) (VHDL-1241) ocram_sdp.mem is not declared
    ERROR - D:/git/PoC/src/mem/ocram/ocram_tdp.vhdl(82,3-82,11) (VHDL-1363) unknown actual generic literal value ocram_sdp.mem for generic filename ignored
    ERROR - D:/git/PoC/src/mem/ocram/ocram_tdp.vhdl(82,3-82,11) (VHDL-1081) formal filename has no actual or default value
    INFO - D:/git/PoC/src/mem/ocram/ocram_tdp.vhdl(78,8-78,17) (VHDL-1067) elaborating ocram_tdp(rtl)
    INFO - D:/git/PoC/src/mem/ocram/ocram_tdp.vhdl(78,8-78,17) (VHDL-1068) elaboration of entity ocram_tdp failed

    It's the same when I escape the dot with \.

  2. A_BITS=10;D_BITS=32;FILENAME="ocram_sdp.mem"
    This results in a wrong number of arguments error.

    -sdc option: SDC file input not used.
    -lpf option: Output file option is ON.
    ERROR - Wrong number of arguments for -hdl_param. Must have <name, value> pairs.
    Done: error code 2

  3. Setting only A_BITS=10;D_BITS=32 by HDL Parameters and setting FILENAME via default value in the generic section, works fine.

The Lattice Diamond 3.6 User Guide has no reference to the keywords "HDL" and/or "param(eter)".

  • How can I pass strings to the top-level entity, if possible?
  • Is there a separate LSE User Guide?
Paebbels
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  • First question : if you embed the filename directly in the code, does Lattice support it? (presumably, initialising a ROM from that file during synthesis). If not, it doesn't HAVE to support strings as generics... –  Dec 21 '15 at 13:26
  • If I set the file name as a default value in the generic section, then there are no complains. LSE can read files and generates a memory initialization matrix for my ocram. – Paebbels Dec 21 '15 at 13:37
  • Okay, good. Two further thoughts... (1) Simplest possible testcase of a string generic and an Assert/Report. If you can show a default value works but an override doesn't, ... webcase, it feels like a tool bug. (2) Actually, 3 further thoughts... Does the override work in a wrapper VHDL file but not the command line options? Just to localise the issue for the webcase. And (3) At some point, give up and workaround ... such as export the string from a tiny package instead of a generic. –  Dec 21 '15 at 13:47
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    I'll not cry if it doesn't work or I don't find a workaround ... it was just a idea :). I'm a bit confused by the last error message noting that a pair is required. Is it just a internal KeyValuePair notation from C++,Java,C# or whatever or is my syntax wrong? I tried other delimiters and other escape signs, but nothing works, some let Diamond crash *ups*. Correct parameters are reported in the Lattice LSE report as follows: `-hdl_param: name = A_BITS, value = 10` – Paebbels Dec 21 '15 at 13:54
  • Is this just the Lint checker or is this the Synthesis tool? I have found that the Lint checker fails on strings and some related string operations, but that they're able to go through Synthesis OK. – Russell Dec 21 '15 at 13:55
  • The Linter has no problem: a) save files b) linter checks every think c) some minor warnings, but no error. When I start compiling the above errors occur. – Paebbels Dec 21 '15 at 13:58
  • Looks like a bug in the Lattice Synthesis tool (LSE) with respect to HDL Parameters values of string type, since Synplify Pro handles HDL Parameters values of string type correctly, and assign in VHDL files using LSE also works. For workaround, maybe give the parameter value through a package if using LSE, or change to Synplify. – Morten Zilmer Dec 21 '15 at 13:59
  • Sounds like somebody left the `-hdl_params` option parser unfinished. In which case the answer to (2) is yes. If so, worth reporting. –  Dec 21 '15 at 14:00
  • Thanks so far. I'll ask Lattice/report it. At least I can say I needed more then 24h to find a bug in this VHDL tool :) Vivado < 1h; ModelSim < 4h; ... Are there good payed jobs for bug hunting in HDL tools? ... and YES, I know that I use not so common features of the language ;) – Paebbels Dec 21 '15 at 14:28
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    IEEE Std 1076-2008 14.2 Elaboration of a design hierarchy para 7 "An implementation may allow, but is not required to allow, a design entity at the root of a design hierarchy to have generics and ports. If an implementation allows these top-level interface objects, it may restrict their allowed forms (that is, whether they are allowed to be interface types, subprograms, packages, or objects), and, in the case of interface objects, their allowed types and modes in an implementation-defined manner." (Yes, synthesis elaborates). Little reason to support strings for synthesis, not a bug. –  Dec 21 '15 at 16:18
  • @user1155120 Ok, it's no bug from the view of the VHDL standard. The question is, what did the developers intend. For example when I enclose the value in quotes, Diamond crashes on file save and crashes on every new start until I removed the faulty settings line from the project file. I wrote a question to the Lattice support and asked to clarify the syntax of the `-hdl_param` option. I also asked if strings are supported. – Paebbels Dec 21 '15 at 16:42
  • If you've encountered a crash case it's safe to bet you're outside the vendor's intended design flow. Supporting features other vendors do is great for increasing market share. Supporting features allowing portability to other vendors not so much. Your intentions and theirs don't necessarily align. –  Dec 21 '15 at 17:12

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