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I have an FPGA project with multiple VHDL files (all compile with no errors), written in Lattice's Diamond software. The problem is when I go to assign pins all I see is the inputs and outputs of one VHDL file. If I delete that file, I see another, the netlist analyzer has the same behavior.

Is it possible to have multiple VHDL files within the same project or must I write everything in one VHDL file?

Paebbels
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user169808
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1 Answers1

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A hardware description language describes a design hierarchy. Each design unit, component or module is stored in a separate HDL file. In your case in different VHDL files. The top most VHDL design unit (entity) is called the top-level of your hierarchy. Only that file's ports can be assigned to device pins. All other ports of subordinate design units must be assigned by port maps in instantiations.

It's not a fault nor error of your tool. You should again about building design hierarchies and how to instantiate entities or components.

Paebbels
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  • There are synthesis tools that allow instantiating IO Cells and using attributes to embed device pins other than the top level of your hierarchy (and require a hierarchy none the less). See [Solved: Assigning FPGA pins in a VHDL submodule - Community Forums](https://forums.xilinx.com/t5/Virtex-Family-FPGAs/Assigning-FPGA-pins-in-a-VHDL-submodule/td-p/27225) for example. –  Aug 20 '17 at 21:25
  • @user1155120 If you take my answer by word, you'll notice that I said, only top-level (VHDL) ports can be assigned to I/O pins, that does not forbid inner cells like `IPAD`s and `OPAD`s to be mapped to pins, but they are no ports as in VHDL ports :). As far as I researched that trick to hide some complexity in my designs some years ago, I found some disadvantages. E.g. a design can not be without an output port or a lot of warnings because an *PAD is a black box for many compilation and transformation steps. – Paebbels Aug 20 '17 at 23:21
  • Besides the misplaced modifier ("Only") being ambiguous 14.2 Elaboration of a design hierarchy, para 7 (in part): "An implementation may allow, but is not required to allow, a design entity at the root of a design hierarchy to have generics and ports...." It may be reckless to make up 'rules' of use contrary to the standard (Xilinx isn't the only one supporting IO cell instantiation). The operative part of your answer is that the OP needs his design in a single hierarchy. –  Aug 21 '17 at 05:41