Lattice Diamond: Setting up a clock

Question

I'm working on learning Verilog and working with CPLDs and I'm stuck. The code I wrote toggles an LED, but I keep getting warnings during synthesis.

//toggles LED on and off after 1000000 clock cycles

module LEDON(
LED,
clk
);

output LED;
reg LED;

input clk ;
wire clk;

reg [31:0] count;
wire count_max = 32'd1_000_000;

assign count_nxt = (count >= count_max) ? 32'd0 : count + 32'd1;
assign led_state_nxt = (count == count_max) ? ~LED : LED;

always @(posedge clk)

begin
    count <= count_nxt;
    LED <= led_state_nxt;

end

endmodule

I get these warnings:

@W: MT420 |Found inferred clock LEDON|clk with period 1000.00ns. Please declare a user-defined clock on object "p:clk"
WARNING - map: C:/Documents and Settings/belo/Desktop/LedOn2/LedON2.lpf (4): Error in FREQUENCY NET "clk" 2.080000 MHz ;
WARNING - map: Preference parsing results: 1 semantic error detected
WARNING - map: There are errors in the preference file, "C:/Documents and Settings/belo/Desktop/LedOn2/LedON2.lpf".
WARNING - map: There are semantic errors in the preference file, "C:/Documents and Settings/belo/Desktop/LedOn2/LedON2.prf".

My LPF file looks like this:

BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
LOCATE COMP "LED" SITE "41" ;
FREQUENCY NET "clk" 2.08 MHz ;

So does anyone know how to fix these clock warnings?

I managed to fix most of the warnings by changing the code in my LPF file from: FREQUENCY NET "clk" 2.08 MHz ; to FREQUENCY PORT "clk" 2.08 MHz ; But the LED still doesn't blink. — Ben Elo, Jul 02 '12 at 17:36
Errors Now: @W: CL189 :"C:\Documents and Settings\belo\Desktop\LedOn2\LEDON.v":20:0:20:5|Register bit count[2] is always 0, optimizing ... @W: CL189 :"C:\Documents and Settings\belo\Desktop\LedOn2\LEDON.v":20:0:20:5|Register bit count[1] is always 0, optimizing ... @W: CL189 :"C:\Documents and Settings\belo\Desktop\LedOn2\LEDON.v":20:0:20:5|Register bit count[0] is always 0, optimizing ... @W: MT420 |Found inferred clock LEDON|clk with period 1000.00ns. Please declare a user-defined clock on object "p:clk" — Ben Elo, Jul 02 '12 at 18:01

score 1 · Accepted Answer · answered Jul 03 '12 at 06:34

I'm not sure if this line: "wire count_max = 32'd1_000_000;" is synthesisable. It might be being ignored except in simulation (this could depend on your tool chain - it's not synthesisable for an ASIC, but for an FPGA ... maybe!!).

The line count>= count_max is comparing count to 0 (and not count max) and thus this is being optomised away (see warnings). This is why it's managed to synthesise but not do anything.

There are multiple solutions. 1) Use a parameter instead (it's like a const in C++ or #define in C):

parameter count_max = 32'd1_000_000;

2) Just use a smaller counter and toggle when it overflows

reg [16:0] count; // counts 131,072 cycles

assign led_next = (count == 0 ? ~LED : LED);
always @(posedge clk)
begin
    count <= count + 1;
    LED <= led_next;
end

score 1 · Answer 2 · answered Dec 22 '16 at 12:35

Solving your first warning could be done by making a SDC constraint file telling which clock speed you wish to have.

Here is an example for creating a clock that runs at approximately 2.08 MHz:

create_clock  -period 480.769 -name {clk} [get_ports {clk}]

Where the period is in ns. If the clock you want to constraint is not a input you can use get_nets instead of get_ports.

Lattice Diamond: Setting up a clock

2 Answers2